Finite State Machine FSM

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I understand how to make state diagram and make combinational logic (gates) to get a boolean equation for the next state bits and the output bit,



but what is the function of ROM here ?



enter image description here






verilog shift-register register state-machines rom







share|improve this question

























    up vote
    1
    down vote

    favorite












    I understand how to make state diagram and make combinational logic (gates) to get a boolean equation for the next state bits and the output bit,



    but what is the function of ROM here ?



    enter image description here






    verilog shift-register register state-machines rom







    share|improve this question























      up vote
      1
      down vote

      favorite









      up vote
      1
      down vote

      favorite











      I understand how to make state diagram and make combinational logic (gates) to get a boolean equation for the next state bits and the output bit,



      but what is the function of ROM here ?



      enter image description here






      verilog shift-register register state-machines rom







      share|improve this question













      I understand how to make state diagram and make combinational logic (gates) to get a boolean equation for the next state bits and the output bit,



      but what is the function of ROM here ?



      enter image description here






      verilog shift-register register state-machines rom




      verilog shift-register register state-machines rom






      share|improve this question













      share|improve this question











      share|improve this question




      share|improve this question










      asked 3 hours ago









      Aren dg

      62




      62




















          2 Answers
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          Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits.



          When one builds a state machine using standard parts, he probably appreciates a construction where all logic gates in the state transition & output logic are replaced by a single easily programmable IC.



          I would add buffer latches to input and output bits to keep sure that inputs are read and outputs are updated in sync, the output bits should in the rom should be surely settled before they are used.






          share|improve this answer






















          • +1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
            – Sparky256
            1 hour ago


















          up vote
          2
          down vote













          This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are equivalent to pages of read-only memory where the inputs are the address and the outputs are the content of the memory.






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            up vote
            3
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            Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits.



            When one builds a state machine using standard parts, he probably appreciates a construction where all logic gates in the state transition & output logic are replaced by a single easily programmable IC.



            I would add buffer latches to input and output bits to keep sure that inputs are read and outputs are updated in sync, the output bits should in the rom should be surely settled before they are used.






            share|improve this answer






















            • +1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
              – Sparky256
              1 hour ago















            up vote
            3
            down vote













            Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits.



            When one builds a state machine using standard parts, he probably appreciates a construction where all logic gates in the state transition & output logic are replaced by a single easily programmable IC.



            I would add buffer latches to input and output bits to keep sure that inputs are read and outputs are updated in sync, the output bits should in the rom should be surely settled before they are used.






            share|improve this answer






















            • +1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
              – Sparky256
              1 hour ago













            up vote
            3
            down vote










            up vote
            3
            down vote









            Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits.



            When one builds a state machine using standard parts, he probably appreciates a construction where all logic gates in the state transition & output logic are replaced by a single easily programmable IC.



            I would add buffer latches to input and output bits to keep sure that inputs are read and outputs are updated in sync, the output bits should in the rom should be surely settled before they are used.






            share|improve this answer














            Rom(=Read only memory) is a brute force (=absolutely non-minimized) way to implement a combinatoric circuit. Current state bits and inputs together are address, the data stored into that address contains the next state and possible output bits which both can depend on current state and input bits.



            When one builds a state machine using standard parts, he probably appreciates a construction where all logic gates in the state transition & output logic are replaced by a single easily programmable IC.



            I would add buffer latches to input and output bits to keep sure that inputs are read and outputs are updated in sync, the output bits should in the rom should be surely settled before they are used.







            share|improve this answer














            share|improve this answer



            share|improve this answer








            edited 3 hours ago

























            answered 3 hours ago









            user287001

            8,3581415




            8,3581415











            • +1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
              – Sparky256
              1 hour ago

















            • +1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
              – Sparky256
              1 hour ago
















            +1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
            – Sparky256
            1 hour ago





            +1 for solid answer. That latched output was called a "Pipeline". Back in the 1980's we would program 4 eproms so we had 32 bits of control lines in the pipeline. It controls ALU, memory and device IO, conditional jumps, etc.
            – Sparky256
            1 hour ago













            up vote
            2
            down vote













            This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are equivalent to pages of read-only memory where the inputs are the address and the outputs are the content of the memory.






            share|improve this answer
























              up vote
              2
              down vote













              This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are equivalent to pages of read-only memory where the inputs are the address and the outputs are the content of the memory.






              share|improve this answer






















                up vote
                2
                down vote










                up vote
                2
                down vote









                This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are equivalent to pages of read-only memory where the inputs are the address and the outputs are the content of the memory.






                share|improve this answer












                This look like a general representation of sequential logic. It could be Read Only Memory: Any boolean function or logic gates combination can be implemented as a look-up table, and look-up tables are equivalent to pages of read-only memory where the inputs are the address and the outputs are the content of the memory.







                share|improve this answer












                share|improve this answer



                share|improve this answer










                answered 3 hours ago









                pserra

                511211




                511211



























                     

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