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How do accelerators and CPU cards work on the Apple II?
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An Amiga 1200 exposes the entire CPU bus on the expansion port, so that an accelerator only needs to assert BR which causes the onboard CPU to stop all computation and electrically disconnect from the bus entirely, and then wait for BG which should mean that the CPU on the accelerator is ready to consider itself the Master Of The Bus.
Or something.
And in the case of the Commodore 64, the VIC-II asserts the BA so that it can completely take over the bus.
The thing is, I don't see anything like BA, BR or BG on the Apple II slot. So what's unclear to me is, when a CPU is added to the Apple II, how it takes over the control. I suppose it would be problematic if the 6502 was still running. Take the Z-80 Softcard. It's got a CPU obviously, and a handful of TTL for glue logic. But it does not have any RAM. It just uses the same RAM which is already installed in the computer. This means that if some application is running on the Z80, its state might get clobbered by whatever the 6502 is doing.
TL;DR how do CPU cards work on the Apple II if there's no way to take the bus over?
apple-ii cpu
asked 2 hours ago
Wilson
9,358543115
add a comment |Â
up vote
1
down vote
favorite
An Amiga 1200 exposes the entire CPU bus on the expansion port, so that an accelerator only needs to assert BR which causes the onboard CPU to stop all computation and electrically disconnect from the bus entirely, and then wait for BG which should mean that the CPU on the accelerator is ready to consider itself the Master Of The Bus.
Or something.
And in the case of the Commodore 64, the VIC-II asserts the BA so that it can completely take over the bus.
The thing is, I don't see anything like BA, BR or BG on the Apple II slot. So what's unclear to me is, when a CPU is added to the Apple II, how it takes over the control. I suppose it would be problematic if the 6502 was still running. Take the Z-80 Softcard. It's got a CPU obviously, and a handful of TTL for glue logic. But it does not have any RAM. It just uses the same RAM which is already installed in the computer. This means that if some application is running on the Z80, its state might get clobbered by whatever the 6502 is doing.
TL;DR how do CPU cards work on the Apple II if there's no way to take the bus over?
apple-ii cpu
asked 2 hours ago
Wilson
9,358543115
I can see thatPHI1andPHI2are available on the slot, but these are presumably outputs, not inputs.
– Wilson
2 hours ago
Isn't that exact what theDMAsignals are for, as in retrocomputing.stackexchange.com/questions/5633/… ? Asserting DMA is supposed to halt and isolate the CPU such that the card now gets ownership of RAM.
– Tommy
1 hour ago
add a comment |Â
up vote
1
down vote
favorite
up vote
1
down vote
favorite
An Amiga 1200 exposes the entire CPU bus on the expansion port, so that an accelerator only needs to assert BR which causes the onboard CPU to stop all computation and electrically disconnect from the bus entirely, and then wait for BG which should mean that the CPU on the accelerator is ready to consider itself the Master Of The Bus.
Or something.
And in the case of the Commodore 64, the VIC-II asserts the BA so that it can completely take over the bus.
The thing is, I don't see anything like BA, BR or BG on the Apple II slot. So what's unclear to me is, when a CPU is added to the Apple II, how it takes over the control. I suppose it would be problematic if the 6502 was still running. Take the Z-80 Softcard. It's got a CPU obviously, and a handful of TTL for glue logic. But it does not have any RAM. It just uses the same RAM which is already installed in the computer. This means that if some application is running on the Z80, its state might get clobbered by whatever the 6502 is doing.
TL;DR how do CPU cards work on the Apple II if there's no way to take the bus over?
apple-ii cpu
asked 2 hours ago
Wilson
9,358543115
An Amiga 1200 exposes the entire CPU bus on the expansion port, so that an accelerator only needs to assert BR which causes the onboard CPU to stop all computation and electrically disconnect from the bus entirely, and then wait for BG which should mean that the CPU on the accelerator is ready to consider itself the Master Of The Bus.
Or something.
And in the case of the Commodore 64, the VIC-II asserts the BA so that it can completely take over the bus.
The thing is, I don't see anything like BA, BR or BG on the Apple II slot. So what's unclear to me is, when a CPU is added to the Apple II, how it takes over the control. I suppose it would be problematic if the 6502 was still running. Take the Z-80 Softcard. It's got a CPU obviously, and a handful of TTL for glue logic. But it does not have any RAM. It just uses the same RAM which is already installed in the computer. This means that if some application is running on the Z80, its state might get clobbered by whatever the 6502 is doing.
TL;DR how do CPU cards work on the Apple II if there's no way to take the bus over?
apple-ii cpu
apple-ii cpu
asked 2 hours ago
Wilson
9,358543115
asked 2 hours ago
Wilson
9,358543115
asked 2 hours ago
Wilson
9,358543115
asked 2 hours ago
Wilson
9,358543115
asked 2 hours ago
Wilson
9,358543115
9,358543115
I can see thatPHI1andPHI2are available on the slot, but these are presumably outputs, not inputs.
– Wilson
2 hours ago
Isn't that exact what theDMAsignals are for, as in retrocomputing.stackexchange.com/questions/5633/… ? Asserting DMA is supposed to halt and isolate the CPU such that the card now gets ownership of RAM.
– Tommy
1 hour ago
add a comment |Â
I can see thatPHI1andPHI2are available on the slot, but these are presumably outputs, not inputs.
– Wilson
2 hours ago
Isn't that exact what theDMAsignals are for, as in retrocomputing.stackexchange.com/questions/5633/… ? Asserting DMA is supposed to halt and isolate the CPU such that the card now gets ownership of RAM.
– Tommy
1 hour ago
I can see that
PHI1 and PHI2 are available on the slot, but these are presumably outputs, not inputs.– Wilson
2 hours ago
I can see that
PHI1 and PHI2 are available on the slot, but these are presumably outputs, not inputs.– Wilson
2 hours ago
Isn't that exact what the
DMA signals are for, as in retrocomputing.stackexchange.com/questions/5633/… ? Asserting DMA is supposed to halt and isolate the CPU such that the card now gets ownership of RAM.– Tommy
1 hour ago
Isn't that exact what the
DMA signals are for, as in retrocomputing.stackexchange.com/questions/5633/… ? Asserting DMA is supposed to halt and isolate the CPU such that the card now gets ownership of RAM.– Tommy
1 hour ago
add a comment |Â
1 Answer
1
active
oldest
votes
up vote
4
down vote
how do CPU cards work on the Apple II if there's no way to take the bus over?
Thats what /DMA (pin 22) is good for. It halts the CPU and tristates the bus. Now any card can take over.
Unlike it's daddy, the 6800 (and many other CPUs), the 6502 can be halted in at any clock state by pulling /RDY. It will extend the actual cycle (*1). This doesn't tristate the bus or anything else, and is primary ment to allow singlesteping and support slow memory, but can do DMA as well. Not very sophisticated, but it does the job.
On the Apple II Woz' added a bunch of buffers to tristate the bus when needed. When DMA gets pulled, the CPU will get its /RDY pulled and the buffers will tristate the address/data lines.`
Video update and RAM refresh will continue as before - The Card May Only Access the Bus During Phi0, even with DMA pulled continous, as video and refresh logic will access the RAM during 'Phi1` (*2)
But there are Apples fited with a NMOS 6502 (*3). Due its dynamic nature (*4) it needs to do some workout to keep the register content intact. In general, one successful cycle every 10 cycles will do it (*5,6). Each card needs a apropriate solution.
This can be some counter halting the card every 4th, 8th or 16th cycle and hand one cycle to the 6502, or maybe there are times where the card's CPU doesn't need the bus, which may be always handed over to the 6502 (*7)
The Z80 card is doing the later, as the CPU needs an internal cycle after each opcode fetch (signaled by M1), where no bus acvity happens. relinquishing that to the 6502 makes it happen often enough (*8) without throttleing the Z80 at all.
*1 - Well, it shouldn't be pulled within a write cycle, as the CPU will not repeat such. Then again, when pulled during Phi1, it will always stop.
*2 - So no, there is no chance to access the RAM at 2 MHz from an I/O card. Would have been nice, wouldn't it?
*3 - so if the card needs only to work with a CMOS like in an enhanced IIe, it will be possible to use all cycles.
*4 - The registers are basicly dynamic memory and need refresh.
*5 - It's said that a MOS/Rockwell chip can do 10-17 cycles without, while a Synertec is guaranteed to do 40.
*6 - yes, this means the 6502 is active running at maybe 5-10% speed. So here's your chance for real dual CPU action.
*7 - If these holes are common, the 6502 may get even more usable CPU time.
*8 - Well, going by the books there are some instructions (most notably all modifying with index register + displacement addressing like INC or RES) wich need 23 cycles. Since the Z80 runs at double the 6502 clock (*9), this ends up being 12 cycles, thus still on the good side.
*9 - Well, it's way more complicted than that, but also a great example of clever hardware design. The Z80 rund from the Apples 7 MHz clock, divided by two but only during Phi1 which will result in a full cycle in the first 4/7th of Phi1 plus one that stretches over the rest and all of Phi0. Effective clock speed is 2.04 MHz, but some instructions get extended by oe of the 'short' cycles to synchronize for memory access.
answered 1 hour ago
Raffzahn
39.7k488160
Ah,DMAis maybe a misnomer then. Does the CPU card need to implement some DRAM refresh whileDMAis asserted?
– Wilson
1 hour ago
1
It's not technically a misnomer; you want direct access to memory, you get direct access to memory. Though I guess that the fact of the 6502 being disabled is only an implication?
– Tommy
58 mins ago
So you're limited to accessing the system's RAM at around 1 MHz? Perhaps, some cards had their own memory onboard to access it at a faster speed, like some Amiga accelerators do. That would have been right dandy for the Microsoft Z80 one if there was enough space/money.
– Wilson
20 mins ago
add a comment |Â
1 Answer
1
active
oldest
votes
1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
up vote
4
down vote
how do CPU cards work on the Apple II if there's no way to take the bus over?
Thats what /DMA (pin 22) is good for. It halts the CPU and tristates the bus. Now any card can take over.
Unlike it's daddy, the 6800 (and many other CPUs), the 6502 can be halted in at any clock state by pulling /RDY. It will extend the actual cycle (*1). This doesn't tristate the bus or anything else, and is primary ment to allow singlesteping and support slow memory, but can do DMA as well. Not very sophisticated, but it does the job.
On the Apple II Woz' added a bunch of buffers to tristate the bus when needed. When DMA gets pulled, the CPU will get its /RDY pulled and the buffers will tristate the address/data lines.`
Video update and RAM refresh will continue as before - The Card May Only Access the Bus During Phi0, even with DMA pulled continous, as video and refresh logic will access the RAM during 'Phi1` (*2)
But there are Apples fited with a NMOS 6502 (*3). Due its dynamic nature (*4) it needs to do some workout to keep the register content intact. In general, one successful cycle every 10 cycles will do it (*5,6). Each card needs a apropriate solution.
This can be some counter halting the card every 4th, 8th or 16th cycle and hand one cycle to the 6502, or maybe there are times where the card's CPU doesn't need the bus, which may be always handed over to the 6502 (*7)
The Z80 card is doing the later, as the CPU needs an internal cycle after each opcode fetch (signaled by M1), where no bus acvity happens. relinquishing that to the 6502 makes it happen often enough (*8) without throttleing the Z80 at all.
*1 - Well, it shouldn't be pulled within a write cycle, as the CPU will not repeat such. Then again, when pulled during Phi1, it will always stop.
*2 - So no, there is no chance to access the RAM at 2 MHz from an I/O card. Would have been nice, wouldn't it?
*3 - so if the card needs only to work with a CMOS like in an enhanced IIe, it will be possible to use all cycles.
*4 - The registers are basicly dynamic memory and need refresh.
*5 - It's said that a MOS/Rockwell chip can do 10-17 cycles without, while a Synertec is guaranteed to do 40.
*6 - yes, this means the 6502 is active running at maybe 5-10% speed. So here's your chance for real dual CPU action.
*7 - If these holes are common, the 6502 may get even more usable CPU time.
*8 - Well, going by the books there are some instructions (most notably all modifying with index register + displacement addressing like INC or RES) wich need 23 cycles. Since the Z80 runs at double the 6502 clock (*9), this ends up being 12 cycles, thus still on the good side.
*9 - Well, it's way more complicted than that, but also a great example of clever hardware design. The Z80 rund from the Apples 7 MHz clock, divided by two but only during Phi1 which will result in a full cycle in the first 4/7th of Phi1 plus one that stretches over the rest and all of Phi0. Effective clock speed is 2.04 MHz, but some instructions get extended by oe of the 'short' cycles to synchronize for memory access.
answered 1 hour ago
Raffzahn
39.7k488160
Ah,DMAis maybe a misnomer then. Does the CPU card need to implement some DRAM refresh whileDMAis asserted?
– Wilson
1 hour ago
1
It's not technically a misnomer; you want direct access to memory, you get direct access to memory. Though I guess that the fact of the 6502 being disabled is only an implication?
– Tommy
58 mins ago
So you're limited to accessing the system's RAM at around 1 MHz? Perhaps, some cards had their own memory onboard to access it at a faster speed, like some Amiga accelerators do. That would have been right dandy for the Microsoft Z80 one if there was enough space/money.
– Wilson
20 mins ago
add a comment |Â
up vote
4
down vote
how do CPU cards work on the Apple II if there's no way to take the bus over?
Thats what /DMA (pin 22) is good for. It halts the CPU and tristates the bus. Now any card can take over.
Unlike it's daddy, the 6800 (and many other CPUs), the 6502 can be halted in at any clock state by pulling /RDY. It will extend the actual cycle (*1). This doesn't tristate the bus or anything else, and is primary ment to allow singlesteping and support slow memory, but can do DMA as well. Not very sophisticated, but it does the job.
On the Apple II Woz' added a bunch of buffers to tristate the bus when needed. When DMA gets pulled, the CPU will get its /RDY pulled and the buffers will tristate the address/data lines.`
Video update and RAM refresh will continue as before - The Card May Only Access the Bus During Phi0, even with DMA pulled continous, as video and refresh logic will access the RAM during 'Phi1` (*2)
But there are Apples fited with a NMOS 6502 (*3). Due its dynamic nature (*4) it needs to do some workout to keep the register content intact. In general, one successful cycle every 10 cycles will do it (*5,6). Each card needs a apropriate solution.
This can be some counter halting the card every 4th, 8th or 16th cycle and hand one cycle to the 6502, or maybe there are times where the card's CPU doesn't need the bus, which may be always handed over to the 6502 (*7)
The Z80 card is doing the later, as the CPU needs an internal cycle after each opcode fetch (signaled by M1), where no bus acvity happens. relinquishing that to the 6502 makes it happen often enough (*8) without throttleing the Z80 at all.
*1 - Well, it shouldn't be pulled within a write cycle, as the CPU will not repeat such. Then again, when pulled during Phi1, it will always stop.
*2 - So no, there is no chance to access the RAM at 2 MHz from an I/O card. Would have been nice, wouldn't it?
*3 - so if the card needs only to work with a CMOS like in an enhanced IIe, it will be possible to use all cycles.
*4 - The registers are basicly dynamic memory and need refresh.
*5 - It's said that a MOS/Rockwell chip can do 10-17 cycles without, while a Synertec is guaranteed to do 40.
*6 - yes, this means the 6502 is active running at maybe 5-10% speed. So here's your chance for real dual CPU action.
*7 - If these holes are common, the 6502 may get even more usable CPU time.
*8 - Well, going by the books there are some instructions (most notably all modifying with index register + displacement addressing like INC or RES) wich need 23 cycles. Since the Z80 runs at double the 6502 clock (*9), this ends up being 12 cycles, thus still on the good side.
*9 - Well, it's way more complicted than that, but also a great example of clever hardware design. The Z80 rund from the Apples 7 MHz clock, divided by two but only during Phi1 which will result in a full cycle in the first 4/7th of Phi1 plus one that stretches over the rest and all of Phi0. Effective clock speed is 2.04 MHz, but some instructions get extended by oe of the 'short' cycles to synchronize for memory access.
answered 1 hour ago
Raffzahn
39.7k488160
Ah,DMAis maybe a misnomer then. Does the CPU card need to implement some DRAM refresh whileDMAis asserted?
– Wilson
1 hour ago
1
It's not technically a misnomer; you want direct access to memory, you get direct access to memory. Though I guess that the fact of the 6502 being disabled is only an implication?
– Tommy
58 mins ago
So you're limited to accessing the system's RAM at around 1 MHz? Perhaps, some cards had their own memory onboard to access it at a faster speed, like some Amiga accelerators do. That would have been right dandy for the Microsoft Z80 one if there was enough space/money.
– Wilson
20 mins ago
add a comment |Â
up vote
4
down vote
up vote
4
down vote
how do CPU cards work on the Apple II if there's no way to take the bus over?
Thats what /DMA (pin 22) is good for. It halts the CPU and tristates the bus. Now any card can take over.
Unlike it's daddy, the 6800 (and many other CPUs), the 6502 can be halted in at any clock state by pulling /RDY. It will extend the actual cycle (*1). This doesn't tristate the bus or anything else, and is primary ment to allow singlesteping and support slow memory, but can do DMA as well. Not very sophisticated, but it does the job.
On the Apple II Woz' added a bunch of buffers to tristate the bus when needed. When DMA gets pulled, the CPU will get its /RDY pulled and the buffers will tristate the address/data lines.`
Video update and RAM refresh will continue as before - The Card May Only Access the Bus During Phi0, even with DMA pulled continous, as video and refresh logic will access the RAM during 'Phi1` (*2)
But there are Apples fited with a NMOS 6502 (*3). Due its dynamic nature (*4) it needs to do some workout to keep the register content intact. In general, one successful cycle every 10 cycles will do it (*5,6). Each card needs a apropriate solution.
This can be some counter halting the card every 4th, 8th or 16th cycle and hand one cycle to the 6502, or maybe there are times where the card's CPU doesn't need the bus, which may be always handed over to the 6502 (*7)
The Z80 card is doing the later, as the CPU needs an internal cycle after each opcode fetch (signaled by M1), where no bus acvity happens. relinquishing that to the 6502 makes it happen often enough (*8) without throttleing the Z80 at all.
*1 - Well, it shouldn't be pulled within a write cycle, as the CPU will not repeat such. Then again, when pulled during Phi1, it will always stop.
*2 - So no, there is no chance to access the RAM at 2 MHz from an I/O card. Would have been nice, wouldn't it?
*3 - so if the card needs only to work with a CMOS like in an enhanced IIe, it will be possible to use all cycles.
*4 - The registers are basicly dynamic memory and need refresh.
*5 - It's said that a MOS/Rockwell chip can do 10-17 cycles without, while a Synertec is guaranteed to do 40.
*6 - yes, this means the 6502 is active running at maybe 5-10% speed. So here's your chance for real dual CPU action.
*7 - If these holes are common, the 6502 may get even more usable CPU time.
*8 - Well, going by the books there are some instructions (most notably all modifying with index register + displacement addressing like INC or RES) wich need 23 cycles. Since the Z80 runs at double the 6502 clock (*9), this ends up being 12 cycles, thus still on the good side.
*9 - Well, it's way more complicted than that, but also a great example of clever hardware design. The Z80 rund from the Apples 7 MHz clock, divided by two but only during Phi1 which will result in a full cycle in the first 4/7th of Phi1 plus one that stretches over the rest and all of Phi0. Effective clock speed is 2.04 MHz, but some instructions get extended by oe of the 'short' cycles to synchronize for memory access.
answered 1 hour ago
Raffzahn
39.7k488160
how do CPU cards work on the Apple II if there's no way to take the bus over?
Thats what /DMA (pin 22) is good for. It halts the CPU and tristates the bus. Now any card can take over.
Unlike it's daddy, the 6800 (and many other CPUs), the 6502 can be halted in at any clock state by pulling /RDY. It will extend the actual cycle (*1). This doesn't tristate the bus or anything else, and is primary ment to allow singlesteping and support slow memory, but can do DMA as well. Not very sophisticated, but it does the job.
On the Apple II Woz' added a bunch of buffers to tristate the bus when needed. When DMA gets pulled, the CPU will get its /RDY pulled and the buffers will tristate the address/data lines.`
Video update and RAM refresh will continue as before - The Card May Only Access the Bus During Phi0, even with DMA pulled continous, as video and refresh logic will access the RAM during 'Phi1` (*2)
But there are Apples fited with a NMOS 6502 (*3). Due its dynamic nature (*4) it needs to do some workout to keep the register content intact. In general, one successful cycle every 10 cycles will do it (*5,6). Each card needs a apropriate solution.
This can be some counter halting the card every 4th, 8th or 16th cycle and hand one cycle to the 6502, or maybe there are times where the card's CPU doesn't need the bus, which may be always handed over to the 6502 (*7)
The Z80 card is doing the later, as the CPU needs an internal cycle after each opcode fetch (signaled by M1), where no bus acvity happens. relinquishing that to the 6502 makes it happen often enough (*8) without throttleing the Z80 at all.
*1 - Well, it shouldn't be pulled within a write cycle, as the CPU will not repeat such. Then again, when pulled during Phi1, it will always stop.
*2 - So no, there is no chance to access the RAM at 2 MHz from an I/O card. Would have been nice, wouldn't it?
*3 - so if the card needs only to work with a CMOS like in an enhanced IIe, it will be possible to use all cycles.
*4 - The registers are basicly dynamic memory and need refresh.
*5 - It's said that a MOS/Rockwell chip can do 10-17 cycles without, while a Synertec is guaranteed to do 40.
*6 - yes, this means the 6502 is active running at maybe 5-10% speed. So here's your chance for real dual CPU action.
*7 - If these holes are common, the 6502 may get even more usable CPU time.
*8 - Well, going by the books there are some instructions (most notably all modifying with index register + displacement addressing like INC or RES) wich need 23 cycles. Since the Z80 runs at double the 6502 clock (*9), this ends up being 12 cycles, thus still on the good side.
*9 - Well, it's way more complicted than that, but also a great example of clever hardware design. The Z80 rund from the Apples 7 MHz clock, divided by two but only during Phi1 which will result in a full cycle in the first 4/7th of Phi1 plus one that stretches over the rest and all of Phi0. Effective clock speed is 2.04 MHz, but some instructions get extended by oe of the 'short' cycles to synchronize for memory access.
answered 1 hour ago
Raffzahn
39.7k488160
edited 8 mins ago
answered 1 hour ago
Raffzahn
39.7k488160
answered 1 hour ago
Raffzahn
39.7k488160
answered 1 hour ago
Raffzahn
39.7k488160
39.7k488160
Ah,DMAis maybe a misnomer then. Does the CPU card need to implement some DRAM refresh whileDMAis asserted?
– Wilson
1 hour ago
1
It's not technically a misnomer; you want direct access to memory, you get direct access to memory. Though I guess that the fact of the 6502 being disabled is only an implication?
– Tommy
58 mins ago
So you're limited to accessing the system's RAM at around 1 MHz? Perhaps, some cards had their own memory onboard to access it at a faster speed, like some Amiga accelerators do. That would have been right dandy for the Microsoft Z80 one if there was enough space/money.
– Wilson
20 mins ago
add a comment |Â
Ah,DMAis maybe a misnomer then. Does the CPU card need to implement some DRAM refresh whileDMAis asserted?
– Wilson
1 hour ago
1
It's not technically a misnomer; you want direct access to memory, you get direct access to memory. Though I guess that the fact of the 6502 being disabled is only an implication?
– Tommy
58 mins ago
So you're limited to accessing the system's RAM at around 1 MHz? Perhaps, some cards had their own memory onboard to access it at a faster speed, like some Amiga accelerators do. That would have been right dandy for the Microsoft Z80 one if there was enough space/money.
– Wilson
20 mins ago
Ah,
DMA is maybe a misnomer then. Does the CPU card need to implement some DRAM refresh while DMA is asserted?– Wilson
1 hour ago
Ah,
DMA is maybe a misnomer then. Does the CPU card need to implement some DRAM refresh while DMA is asserted?– Wilson
1 hour ago
1
1
It's not technically a misnomer; you want direct access to memory, you get direct access to memory. Though I guess that the fact of the 6502 being disabled is only an implication?
– Tommy
58 mins ago
It's not technically a misnomer; you want direct access to memory, you get direct access to memory. Though I guess that the fact of the 6502 being disabled is only an implication?
– Tommy
58 mins ago
So you're limited to accessing the system's RAM at around 1 MHz? Perhaps, some cards had their own memory onboard to access it at a faster speed, like some Amiga accelerators do. That would have been right dandy for the Microsoft Z80 one if there was enough space/money.
– Wilson
20 mins ago
So you're limited to accessing the system's RAM at around 1 MHz? Perhaps, some cards had their own memory onboard to access it at a faster speed, like some Amiga accelerators do. That would have been right dandy for the Microsoft Z80 one if there was enough space/money.
– Wilson
20 mins ago
add a comment |Â
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I can see that
PHI1andPHI2are available on the slot, but these are presumably outputs, not inputs.– Wilson
2 hours ago
Isn't that exact what the
DMAsignals are for, as in retrocomputing.stackexchange.com/questions/5633/… ? Asserting DMA is supposed to halt and isolate the CPU such that the card now gets ownership of RAM.– Tommy
1 hour ago