Mixing
Z80 16-bit I/O port addresses
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The Z80 indirect I/O instructions are a little quirky: the instructions with the standard mnemonic in r, (c) (where r is a stand-in for any of the normal registers) actually puts the register pair bc on the address bus, not just c as implied in the mnemonic, and likewise for out (c), r.
This capability is rarely used, but there are some instances (e.g. the keyboards of the ZX81 and ZXÂ Spectrum use the upper byte to select a row to scan) where it was used to good effect.
Is this behaviour intentional, in order to allow the Z80 to expand beyond the 256 port limit of the 8080 -- in which case, is the reason it wasn't documented known? -- or is it a result of a bug in the processor implementation (presumably a microcode error that wasn't detected prior to release)?
z80
edited 13 mins ago
Peter Mortensen
1475
asked 11 hours ago
Jules
7,66812139
add a comment |Â
up vote
2
down vote
favorite
The Z80 indirect I/O instructions are a little quirky: the instructions with the standard mnemonic in r, (c) (where r is a stand-in for any of the normal registers) actually puts the register pair bc on the address bus, not just c as implied in the mnemonic, and likewise for out (c), r.
This capability is rarely used, but there are some instances (e.g. the keyboards of the ZX81 and ZXÂ Spectrum use the upper byte to select a row to scan) where it was used to good effect.
Is this behaviour intentional, in order to allow the Z80 to expand beyond the 256 port limit of the 8080 -- in which case, is the reason it wasn't documented known? -- or is it a result of a bug in the processor implementation (presumably a microcode error that wasn't detected prior to release)?
z80
edited 13 mins ago
Peter Mortensen
1475
asked 11 hours ago
Jules
7,66812139
add a comment |Â
up vote
2
down vote
favorite
up vote
2
down vote
favorite
The Z80 indirect I/O instructions are a little quirky: the instructions with the standard mnemonic in r, (c) (where r is a stand-in for any of the normal registers) actually puts the register pair bc on the address bus, not just c as implied in the mnemonic, and likewise for out (c), r.
This capability is rarely used, but there are some instances (e.g. the keyboards of the ZX81 and ZXÂ Spectrum use the upper byte to select a row to scan) where it was used to good effect.
Is this behaviour intentional, in order to allow the Z80 to expand beyond the 256 port limit of the 8080 -- in which case, is the reason it wasn't documented known? -- or is it a result of a bug in the processor implementation (presumably a microcode error that wasn't detected prior to release)?
z80
edited 13 mins ago
Peter Mortensen
1475
asked 11 hours ago
Jules
7,66812139
The Z80 indirect I/O instructions are a little quirky: the instructions with the standard mnemonic in r, (c) (where r is a stand-in for any of the normal registers) actually puts the register pair bc on the address bus, not just c as implied in the mnemonic, and likewise for out (c), r.
This capability is rarely used, but there are some instances (e.g. the keyboards of the ZX81 and ZXÂ Spectrum use the upper byte to select a row to scan) where it was used to good effect.
Is this behaviour intentional, in order to allow the Z80 to expand beyond the 256 port limit of the 8080 -- in which case, is the reason it wasn't documented known? -- or is it a result of a bug in the processor implementation (presumably a microcode error that wasn't detected prior to release)?
z80
z80
edited 13 mins ago
Peter Mortensen
1475
asked 11 hours ago
Jules
7,66812139
edited 13 mins ago
Peter Mortensen
1475
asked 11 hours ago
Jules
7,66812139
edited 13 mins ago
Peter Mortensen
1475
edited 13 mins ago
Peter Mortensen
1475
edited 13 mins ago
Peter Mortensen
1475
1475
asked 11 hours ago
Jules
7,66812139
asked 11 hours ago
Jules
7,66812139
asked 11 hours ago
Jules
7,66812139
7,66812139
add a comment |Â
add a comment |Â
3 Answers
3
active
oldest
votes
up vote
5
down vote
Well, the Z-80 CPU documentation that I have, a Zilog Z-80 product spec, PS017801-0602, clearly shows the behavior you noted in your question.
In addition, the traditional I/O instructions, such as:
IN A,(n)
show the address bus as n to A0 ~ A7 and A to A8 ~ A15
Clearly this "feature" is documented. I suspect it was just not used much.
answered 8 hours ago
Peter Camilleri
59628
Both the Sinclair ZX spectrum and the Amstrad CPC used 16 bit port addresses. So the feature was used...
– Martin Rosenau
1 hour ago
add a comment |Â
up vote
2
down vote
Based on the fact that when you build a computer that evaluates the upper 8 address lines on an I/O cycle (and can use 16-bit I/O addresses), you can then unfortunately no longer use the block input and block output commands (as B is used as a repeat count), I think we can safely assume it was not intended that port address evaluation would take A8-A15 into account when the chip was designed.
In case a designer would decide to actually evaluate the upper address lines on an I/O cycle, the fact that OUT <PORT>,A puts the contents of the accumulator on A8-A15 is not very useful, as A would hold the byte to output. OUT (C),A could be useful and actually is used sometimes, like on the ZX-81 and on the Amstrad CPC range that use 16-bit I/O addresses (thus generally inhibiting any use of the former, as well as the block I/O commands). The sad fact that the CPC doesn't really make good use of its "enhanced" 16-bit I/O port address range is a different story, though)
The Zilog Z80 manual of 2016 (!) clearly states
In all Register Indirect input output instructions, including block I/O transfers, the contents of the C Register are transferred to the lower half of the address bus (device address) while the contents of Register B are transferred to the upper half of the address bus.
The same manual also very clearly states in the description of the /IOREQ signal (emphasis mine):
IORQ. Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation.
The same manual shows A0-15 in the description of the I/O cycle and labels this "I/O address", which is, at least, somewhat misleading.
An older (1979) MOSTEK Z80 manual I found, shows only A0-A7 in the I/O cycle diagrams as port address, but does state the fact that register B is put to the upper half of the address bus on an I/O cycle.
I would neither suspect a design bug nor a documentation problem: The behavior is very clearly documented, apparently even in early manuals. It is also implied you simply shouldn't evaluate the upper 8 address lines on an I/O cycle. You still can, but if you do so, you will not be able to make sensible use of some of the I/O instructions.
answered 4 hours ago
tofro
12.3k32671
add a comment |Â
up vote
0
down vote
16bit I/O addressing capability of Z80 is clearly an improvement over 8080 8bit I/O address space.
This capability is rarely used
It was actually extensively used even in 80ies era computers. For example, ZX Spectrum 48k used addresses A15..A8 to select keyboard row to scan when CPU read #xxFE port. ZX Spectrum 128k, in addition, used 16bit I/O ports with addresses like #7FFD, #BFFD and #FFFD.
answered 2 mins ago
lvd
2,162316
add a comment |Â
3 Answers
3
active
oldest
votes
3 Answers
3
active
oldest
votes
active
oldest
votes
active
oldest
votes
up vote
5
down vote
Well, the Z-80 CPU documentation that I have, a Zilog Z-80 product spec, PS017801-0602, clearly shows the behavior you noted in your question.
In addition, the traditional I/O instructions, such as:
IN A,(n)
show the address bus as n to A0 ~ A7 and A to A8 ~ A15
Clearly this "feature" is documented. I suspect it was just not used much.
answered 8 hours ago
Peter Camilleri
59628
Both the Sinclair ZX spectrum and the Amstrad CPC used 16 bit port addresses. So the feature was used...
– Martin Rosenau
1 hour ago
add a comment |Â
up vote
5
down vote
Well, the Z-80 CPU documentation that I have, a Zilog Z-80 product spec, PS017801-0602, clearly shows the behavior you noted in your question.
In addition, the traditional I/O instructions, such as:
IN A,(n)
show the address bus as n to A0 ~ A7 and A to A8 ~ A15
Clearly this "feature" is documented. I suspect it was just not used much.
answered 8 hours ago
Peter Camilleri
59628
Both the Sinclair ZX spectrum and the Amstrad CPC used 16 bit port addresses. So the feature was used...
– Martin Rosenau
1 hour ago
add a comment |Â
up vote
5
down vote
up vote
5
down vote
Well, the Z-80 CPU documentation that I have, a Zilog Z-80 product spec, PS017801-0602, clearly shows the behavior you noted in your question.
In addition, the traditional I/O instructions, such as:
IN A,(n)
show the address bus as n to A0 ~ A7 and A to A8 ~ A15
Clearly this "feature" is documented. I suspect it was just not used much.
answered 8 hours ago
Peter Camilleri
59628
Well, the Z-80 CPU documentation that I have, a Zilog Z-80 product spec, PS017801-0602, clearly shows the behavior you noted in your question.
In addition, the traditional I/O instructions, such as:
IN A,(n)
show the address bus as n to A0 ~ A7 and A to A8 ~ A15
Clearly this "feature" is documented. I suspect it was just not used much.
answered 8 hours ago
Peter Camilleri
59628
answered 8 hours ago
Peter Camilleri
59628
answered 8 hours ago
Peter Camilleri
59628
answered 8 hours ago
Peter Camilleri
59628
59628
Both the Sinclair ZX spectrum and the Amstrad CPC used 16 bit port addresses. So the feature was used...
– Martin Rosenau
1 hour ago
add a comment |Â
Both the Sinclair ZX spectrum and the Amstrad CPC used 16 bit port addresses. So the feature was used...
– Martin Rosenau
1 hour ago
Both the Sinclair ZX spectrum and the Amstrad CPC used 16 bit port addresses. So the feature was used...
– Martin Rosenau
1 hour ago
Both the Sinclair ZX spectrum and the Amstrad CPC used 16 bit port addresses. So the feature was used...
– Martin Rosenau
1 hour ago
add a comment |Â
up vote
2
down vote
Based on the fact that when you build a computer that evaluates the upper 8 address lines on an I/O cycle (and can use 16-bit I/O addresses), you can then unfortunately no longer use the block input and block output commands (as B is used as a repeat count), I think we can safely assume it was not intended that port address evaluation would take A8-A15 into account when the chip was designed.
In case a designer would decide to actually evaluate the upper address lines on an I/O cycle, the fact that OUT <PORT>,A puts the contents of the accumulator on A8-A15 is not very useful, as A would hold the byte to output. OUT (C),A could be useful and actually is used sometimes, like on the ZX-81 and on the Amstrad CPC range that use 16-bit I/O addresses (thus generally inhibiting any use of the former, as well as the block I/O commands). The sad fact that the CPC doesn't really make good use of its "enhanced" 16-bit I/O port address range is a different story, though)
The Zilog Z80 manual of 2016 (!) clearly states
In all Register Indirect input output instructions, including block I/O transfers, the contents of the C Register are transferred to the lower half of the address bus (device address) while the contents of Register B are transferred to the upper half of the address bus.
The same manual also very clearly states in the description of the /IOREQ signal (emphasis mine):
IORQ. Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation.
The same manual shows A0-15 in the description of the I/O cycle and labels this "I/O address", which is, at least, somewhat misleading.
An older (1979) MOSTEK Z80 manual I found, shows only A0-A7 in the I/O cycle diagrams as port address, but does state the fact that register B is put to the upper half of the address bus on an I/O cycle.
I would neither suspect a design bug nor a documentation problem: The behavior is very clearly documented, apparently even in early manuals. It is also implied you simply shouldn't evaluate the upper 8 address lines on an I/O cycle. You still can, but if you do so, you will not be able to make sensible use of some of the I/O instructions.
answered 4 hours ago
tofro
12.3k32671
add a comment |Â
up vote
2
down vote
Based on the fact that when you build a computer that evaluates the upper 8 address lines on an I/O cycle (and can use 16-bit I/O addresses), you can then unfortunately no longer use the block input and block output commands (as B is used as a repeat count), I think we can safely assume it was not intended that port address evaluation would take A8-A15 into account when the chip was designed.
In case a designer would decide to actually evaluate the upper address lines on an I/O cycle, the fact that OUT <PORT>,A puts the contents of the accumulator on A8-A15 is not very useful, as A would hold the byte to output. OUT (C),A could be useful and actually is used sometimes, like on the ZX-81 and on the Amstrad CPC range that use 16-bit I/O addresses (thus generally inhibiting any use of the former, as well as the block I/O commands). The sad fact that the CPC doesn't really make good use of its "enhanced" 16-bit I/O port address range is a different story, though)
The Zilog Z80 manual of 2016 (!) clearly states
In all Register Indirect input output instructions, including block I/O transfers, the contents of the C Register are transferred to the lower half of the address bus (device address) while the contents of Register B are transferred to the upper half of the address bus.
The same manual also very clearly states in the description of the /IOREQ signal (emphasis mine):
IORQ. Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation.
The same manual shows A0-15 in the description of the I/O cycle and labels this "I/O address", which is, at least, somewhat misleading.
An older (1979) MOSTEK Z80 manual I found, shows only A0-A7 in the I/O cycle diagrams as port address, but does state the fact that register B is put to the upper half of the address bus on an I/O cycle.
I would neither suspect a design bug nor a documentation problem: The behavior is very clearly documented, apparently even in early manuals. It is also implied you simply shouldn't evaluate the upper 8 address lines on an I/O cycle. You still can, but if you do so, you will not be able to make sensible use of some of the I/O instructions.
answered 4 hours ago
tofro
12.3k32671
add a comment |Â
up vote
2
down vote
up vote
2
down vote
Based on the fact that when you build a computer that evaluates the upper 8 address lines on an I/O cycle (and can use 16-bit I/O addresses), you can then unfortunately no longer use the block input and block output commands (as B is used as a repeat count), I think we can safely assume it was not intended that port address evaluation would take A8-A15 into account when the chip was designed.
In case a designer would decide to actually evaluate the upper address lines on an I/O cycle, the fact that OUT <PORT>,A puts the contents of the accumulator on A8-A15 is not very useful, as A would hold the byte to output. OUT (C),A could be useful and actually is used sometimes, like on the ZX-81 and on the Amstrad CPC range that use 16-bit I/O addresses (thus generally inhibiting any use of the former, as well as the block I/O commands). The sad fact that the CPC doesn't really make good use of its "enhanced" 16-bit I/O port address range is a different story, though)
The Zilog Z80 manual of 2016 (!) clearly states
In all Register Indirect input output instructions, including block I/O transfers, the contents of the C Register are transferred to the lower half of the address bus (device address) while the contents of Register B are transferred to the upper half of the address bus.
The same manual also very clearly states in the description of the /IOREQ signal (emphasis mine):
IORQ. Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation.
The same manual shows A0-15 in the description of the I/O cycle and labels this "I/O address", which is, at least, somewhat misleading.
An older (1979) MOSTEK Z80 manual I found, shows only A0-A7 in the I/O cycle diagrams as port address, but does state the fact that register B is put to the upper half of the address bus on an I/O cycle.
I would neither suspect a design bug nor a documentation problem: The behavior is very clearly documented, apparently even in early manuals. It is also implied you simply shouldn't evaluate the upper 8 address lines on an I/O cycle. You still can, but if you do so, you will not be able to make sensible use of some of the I/O instructions.
answered 4 hours ago
tofro
12.3k32671
Based on the fact that when you build a computer that evaluates the upper 8 address lines on an I/O cycle (and can use 16-bit I/O addresses), you can then unfortunately no longer use the block input and block output commands (as B is used as a repeat count), I think we can safely assume it was not intended that port address evaluation would take A8-A15 into account when the chip was designed.
In case a designer would decide to actually evaluate the upper address lines on an I/O cycle, the fact that OUT <PORT>,A puts the contents of the accumulator on A8-A15 is not very useful, as A would hold the byte to output. OUT (C),A could be useful and actually is used sometimes, like on the ZX-81 and on the Amstrad CPC range that use 16-bit I/O addresses (thus generally inhibiting any use of the former, as well as the block I/O commands). The sad fact that the CPC doesn't really make good use of its "enhanced" 16-bit I/O port address range is a different story, though)
The Zilog Z80 manual of 2016 (!) clearly states
In all Register Indirect input output instructions, including block I/O transfers, the contents of the C Register are transferred to the lower half of the address bus (device address) while the contents of Register B are transferred to the upper half of the address bus.
The same manual also very clearly states in the description of the /IOREQ signal (emphasis mine):
IORQ. Input/Output Request (output, active Low, tristate). IORQ indicates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation.
The same manual shows A0-15 in the description of the I/O cycle and labels this "I/O address", which is, at least, somewhat misleading.
An older (1979) MOSTEK Z80 manual I found, shows only A0-A7 in the I/O cycle diagrams as port address, but does state the fact that register B is put to the upper half of the address bus on an I/O cycle.
I would neither suspect a design bug nor a documentation problem: The behavior is very clearly documented, apparently even in early manuals. It is also implied you simply shouldn't evaluate the upper 8 address lines on an I/O cycle. You still can, but if you do so, you will not be able to make sensible use of some of the I/O instructions.
answered 4 hours ago
tofro
12.3k32671
edited 4 hours ago
answered 4 hours ago
tofro
12.3k32671
answered 4 hours ago
tofro
12.3k32671
answered 4 hours ago
tofro
12.3k32671
12.3k32671
add a comment |Â
add a comment |Â
up vote
0
down vote
16bit I/O addressing capability of Z80 is clearly an improvement over 8080 8bit I/O address space.
This capability is rarely used
It was actually extensively used even in 80ies era computers. For example, ZX Spectrum 48k used addresses A15..A8 to select keyboard row to scan when CPU read #xxFE port. ZX Spectrum 128k, in addition, used 16bit I/O ports with addresses like #7FFD, #BFFD and #FFFD.
answered 2 mins ago
lvd
2,162316
add a comment |Â
up vote
0
down vote
16bit I/O addressing capability of Z80 is clearly an improvement over 8080 8bit I/O address space.
This capability is rarely used
It was actually extensively used even in 80ies era computers. For example, ZX Spectrum 48k used addresses A15..A8 to select keyboard row to scan when CPU read #xxFE port. ZX Spectrum 128k, in addition, used 16bit I/O ports with addresses like #7FFD, #BFFD and #FFFD.
answered 2 mins ago
lvd
2,162316
add a comment |Â
up vote
0
down vote
up vote
0
down vote
16bit I/O addressing capability of Z80 is clearly an improvement over 8080 8bit I/O address space.
This capability is rarely used
It was actually extensively used even in 80ies era computers. For example, ZX Spectrum 48k used addresses A15..A8 to select keyboard row to scan when CPU read #xxFE port. ZX Spectrum 128k, in addition, used 16bit I/O ports with addresses like #7FFD, #BFFD and #FFFD.
answered 2 mins ago
lvd
2,162316
16bit I/O addressing capability of Z80 is clearly an improvement over 8080 8bit I/O address space.
This capability is rarely used
It was actually extensively used even in 80ies era computers. For example, ZX Spectrum 48k used addresses A15..A8 to select keyboard row to scan when CPU read #xxFE port. ZX Spectrum 128k, in addition, used 16bit I/O ports with addresses like #7FFD, #BFFD and #FFFD.
answered 2 mins ago
lvd
2,162316
answered 2 mins ago
lvd
2,162316
answered 2 mins ago
lvd
2,162316
answered 2 mins ago
lvd
2,162316
2,162316
add a comment |Â
add a comment |Â
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