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6510 IO port initialisation
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TL;DR: With what values are the IO port registers (locations $00 and $01) on the 65120 initialised when it is powered on?
I'm writing a Commodore 64 emulation. The Commodore 64 uses a 6510 microprocessor which has an IO port built in. The IO port is accessed at locations $00 (data direction) and $01 (data). I found lots of documents explaining how the thing works but nothing so far on how it is initialised.
The IO port is the main means of controlling the RAM bank switching, so how it is initialised is critical. For example, if bit 1 of the data direction register is 1 (for output), the ROM between $E000 and $FFFF is controlled by bit 1 of the port (1 = ROM, 0 = RAM).
So on the Commodore 64, unless the data direction register is set for output and the IO port bit 1 is set to 1, there is RAM at the top of the address map and crucially the reset and interrupt vectors are not accessible. However, the designers of the 6510 probably would not do this because they wouldn't have known what IO devices are connected to the port.
The IO port doesn't drive the RAM bank switching directly, but via a PLA so I'm guessing that the DDR and the port are initialised to 0 when the processor switches on and the PLA keeps the ROM selected until the C64 has set the direction and port data correctly. (Maybe there's some sort of tri-state thing going on with a pull up resistor or something.)
Is my assumption correct?
commodore-64 mos-650x
asked 1 hour ago
JeremyP
3,3981925
add a comment |Â
up vote
2
down vote
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TL;DR: With what values are the IO port registers (locations $00 and $01) on the 65120 initialised when it is powered on?
I'm writing a Commodore 64 emulation. The Commodore 64 uses a 6510 microprocessor which has an IO port built in. The IO port is accessed at locations $00 (data direction) and $01 (data). I found lots of documents explaining how the thing works but nothing so far on how it is initialised.
The IO port is the main means of controlling the RAM bank switching, so how it is initialised is critical. For example, if bit 1 of the data direction register is 1 (for output), the ROM between $E000 and $FFFF is controlled by bit 1 of the port (1 = ROM, 0 = RAM).
So on the Commodore 64, unless the data direction register is set for output and the IO port bit 1 is set to 1, there is RAM at the top of the address map and crucially the reset and interrupt vectors are not accessible. However, the designers of the 6510 probably would not do this because they wouldn't have known what IO devices are connected to the port.
The IO port doesn't drive the RAM bank switching directly, but via a PLA so I'm guessing that the DDR and the port are initialised to 0 when the processor switches on and the PLA keeps the ROM selected until the C64 has set the direction and port data correctly. (Maybe there's some sort of tri-state thing going on with a pull up resistor or something.)
Is my assumption correct?
commodore-64 mos-650x
asked 1 hour ago
JeremyP
3,3981925
If a bit in the DDR is set for input, the output is floating. The –LORAM, –HIRAM, and –CHAREN lines have a 3.3kΩ pullup to +5V, so they are high in that case.
– Janka
1 hour ago
The real question is if a –RESET clears the DDR and the port register. IIRC no. With certain games, you could switch off the computer, switch it on again a second later and it would not reset correctly, because the ROM was still turned off.
– Janka
1 hour ago
@Janka that's the internal ROM checking a signature at $8000 to see if a cartridge is plugged in, and transferring control to it if the magic value is there. You can fool this detection by having a cartridge signature in RAM, then as long as the memory contents are intact, the ROM reset routine thinks that there is a cartridge plugged in.
– berendi
39 mins ago
Ah, yes, forgot about that. I used it myself once! So the DDR and port are set to 0 on –RESET.
– Janka
13 mins ago
@Janka The actual check at reset looks for the byte sequence$C3,$C2,$CD,$38,$30at address$8004, and does aJMP ($8000)if present.
– berendi
13 mins ago
add a comment |Â
up vote
2
down vote
favorite
up vote
2
down vote
favorite
TL;DR: With what values are the IO port registers (locations $00 and $01) on the 65120 initialised when it is powered on?
I'm writing a Commodore 64 emulation. The Commodore 64 uses a 6510 microprocessor which has an IO port built in. The IO port is accessed at locations $00 (data direction) and $01 (data). I found lots of documents explaining how the thing works but nothing so far on how it is initialised.
The IO port is the main means of controlling the RAM bank switching, so how it is initialised is critical. For example, if bit 1 of the data direction register is 1 (for output), the ROM between $E000 and $FFFF is controlled by bit 1 of the port (1 = ROM, 0 = RAM).
So on the Commodore 64, unless the data direction register is set for output and the IO port bit 1 is set to 1, there is RAM at the top of the address map and crucially the reset and interrupt vectors are not accessible. However, the designers of the 6510 probably would not do this because they wouldn't have known what IO devices are connected to the port.
The IO port doesn't drive the RAM bank switching directly, but via a PLA so I'm guessing that the DDR and the port are initialised to 0 when the processor switches on and the PLA keeps the ROM selected until the C64 has set the direction and port data correctly. (Maybe there's some sort of tri-state thing going on with a pull up resistor or something.)
Is my assumption correct?
commodore-64 mos-650x
asked 1 hour ago
JeremyP
3,3981925
TL;DR: With what values are the IO port registers (locations $00 and $01) on the 65120 initialised when it is powered on?
I'm writing a Commodore 64 emulation. The Commodore 64 uses a 6510 microprocessor which has an IO port built in. The IO port is accessed at locations $00 (data direction) and $01 (data). I found lots of documents explaining how the thing works but nothing so far on how it is initialised.
The IO port is the main means of controlling the RAM bank switching, so how it is initialised is critical. For example, if bit 1 of the data direction register is 1 (for output), the ROM between $E000 and $FFFF is controlled by bit 1 of the port (1 = ROM, 0 = RAM).
So on the Commodore 64, unless the data direction register is set for output and the IO port bit 1 is set to 1, there is RAM at the top of the address map and crucially the reset and interrupt vectors are not accessible. However, the designers of the 6510 probably would not do this because they wouldn't have known what IO devices are connected to the port.
The IO port doesn't drive the RAM bank switching directly, but via a PLA so I'm guessing that the DDR and the port are initialised to 0 when the processor switches on and the PLA keeps the ROM selected until the C64 has set the direction and port data correctly. (Maybe there's some sort of tri-state thing going on with a pull up resistor or something.)
Is my assumption correct?
commodore-64 mos-650x
commodore-64 mos-650x
asked 1 hour ago
JeremyP
3,3981925
asked 1 hour ago
JeremyP
3,3981925
asked 1 hour ago
JeremyP
3,3981925
asked 1 hour ago
JeremyP
3,3981925
asked 1 hour ago
JeremyP
3,3981925
3,3981925
If a bit in the DDR is set for input, the output is floating. The –LORAM, –HIRAM, and –CHAREN lines have a 3.3kΩ pullup to +5V, so they are high in that case.
– Janka
1 hour ago
The real question is if a –RESET clears the DDR and the port register. IIRC no. With certain games, you could switch off the computer, switch it on again a second later and it would not reset correctly, because the ROM was still turned off.
– Janka
1 hour ago
@Janka that's the internal ROM checking a signature at $8000 to see if a cartridge is plugged in, and transferring control to it if the magic value is there. You can fool this detection by having a cartridge signature in RAM, then as long as the memory contents are intact, the ROM reset routine thinks that there is a cartridge plugged in.
– berendi
39 mins ago
Ah, yes, forgot about that. I used it myself once! So the DDR and port are set to 0 on –RESET.
– Janka
13 mins ago
@Janka The actual check at reset looks for the byte sequence$C3,$C2,$CD,$38,$30at address$8004, and does aJMP ($8000)if present.
– berendi
13 mins ago
add a comment |Â
If a bit in the DDR is set for input, the output is floating. The –LORAM, –HIRAM, and –CHAREN lines have a 3.3kΩ pullup to +5V, so they are high in that case.
– Janka
1 hour ago
The real question is if a –RESET clears the DDR and the port register. IIRC no. With certain games, you could switch off the computer, switch it on again a second later and it would not reset correctly, because the ROM was still turned off.
– Janka
1 hour ago
@Janka that's the internal ROM checking a signature at $8000 to see if a cartridge is plugged in, and transferring control to it if the magic value is there. You can fool this detection by having a cartridge signature in RAM, then as long as the memory contents are intact, the ROM reset routine thinks that there is a cartridge plugged in.
– berendi
39 mins ago
Ah, yes, forgot about that. I used it myself once! So the DDR and port are set to 0 on –RESET.
– Janka
13 mins ago
@Janka The actual check at reset looks for the byte sequence$C3,$C2,$CD,$38,$30at address$8004, and does aJMP ($8000)if present.
– berendi
13 mins ago
If a bit in the DDR is set for input, the output is floating. The –LORAM, –HIRAM, and –CHAREN lines have a 3.3kΩ pullup to +5V, so they are high in that case.
– Janka
1 hour ago
If a bit in the DDR is set for input, the output is floating. The –LORAM, –HIRAM, and –CHAREN lines have a 3.3kΩ pullup to +5V, so they are high in that case.
– Janka
1 hour ago
The real question is if a –RESET clears the DDR and the port register. IIRC no. With certain games, you could switch off the computer, switch it on again a second later and it would not reset correctly, because the ROM was still turned off.
– Janka
1 hour ago
The real question is if a –RESET clears the DDR and the port register. IIRC no. With certain games, you could switch off the computer, switch it on again a second later and it would not reset correctly, because the ROM was still turned off.
– Janka
1 hour ago
@Janka that's the internal ROM checking a signature at $8000 to see if a cartridge is plugged in, and transferring control to it if the magic value is there. You can fool this detection by having a cartridge signature in RAM, then as long as the memory contents are intact, the ROM reset routine thinks that there is a cartridge plugged in.
– berendi
39 mins ago
@Janka that's the internal ROM checking a signature at $8000 to see if a cartridge is plugged in, and transferring control to it if the magic value is there. You can fool this detection by having a cartridge signature in RAM, then as long as the memory contents are intact, the ROM reset routine thinks that there is a cartridge plugged in.
– berendi
39 mins ago
Ah, yes, forgot about that. I used it myself once! So the DDR and port are set to 0 on –RESET.
– Janka
13 mins ago
Ah, yes, forgot about that. I used it myself once! So the DDR and port are set to 0 on –RESET.
– Janka
13 mins ago
@Janka The actual check at reset looks for the byte sequence
$C3,$C2,$CD,$38,$30 at address $8004, and does a JMP ($8000) if present.– berendi
13 mins ago
@Janka The actual check at reset looks for the byte sequence
$C3,$C2,$CD,$38,$30 at address $8004, and does a JMP ($8000) if present.– berendi
13 mins ago
add a comment |Â
1 Answer
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active
oldest
votes
up vote
2
down vote
Yes, your assumption is correct.
Like in any microcontroller design I know of, I/O lines with programmable direction are set to input on reset. The 6510 is no exception, its data direction register at address 0 is set to 0 on reset, all 6 I/O lines become inputs. The circuitry outside the processor includes a pullup resistor on the I/O lines controlling banking, so that they are in a known stable state even if the data direction is set to input.
answered 44 mins ago
berendi
1,289513
add a comment |Â
1 Answer
1
active
oldest
votes
1 Answer
1
active
oldest
votes
active
oldest
votes
active
oldest
votes
up vote
2
down vote
Yes, your assumption is correct.
Like in any microcontroller design I know of, I/O lines with programmable direction are set to input on reset. The 6510 is no exception, its data direction register at address 0 is set to 0 on reset, all 6 I/O lines become inputs. The circuitry outside the processor includes a pullup resistor on the I/O lines controlling banking, so that they are in a known stable state even if the data direction is set to input.
answered 44 mins ago
berendi
1,289513
add a comment |Â
up vote
2
down vote
Yes, your assumption is correct.
Like in any microcontroller design I know of, I/O lines with programmable direction are set to input on reset. The 6510 is no exception, its data direction register at address 0 is set to 0 on reset, all 6 I/O lines become inputs. The circuitry outside the processor includes a pullup resistor on the I/O lines controlling banking, so that they are in a known stable state even if the data direction is set to input.
answered 44 mins ago
berendi
1,289513
add a comment |Â
up vote
2
down vote
up vote
2
down vote
Yes, your assumption is correct.
Like in any microcontroller design I know of, I/O lines with programmable direction are set to input on reset. The 6510 is no exception, its data direction register at address 0 is set to 0 on reset, all 6 I/O lines become inputs. The circuitry outside the processor includes a pullup resistor on the I/O lines controlling banking, so that they are in a known stable state even if the data direction is set to input.
answered 44 mins ago
berendi
1,289513
Yes, your assumption is correct.
Like in any microcontroller design I know of, I/O lines with programmable direction are set to input on reset. The 6510 is no exception, its data direction register at address 0 is set to 0 on reset, all 6 I/O lines become inputs. The circuitry outside the processor includes a pullup resistor on the I/O lines controlling banking, so that they are in a known stable state even if the data direction is set to input.
answered 44 mins ago
berendi
1,289513
answered 44 mins ago
berendi
1,289513
answered 44 mins ago
berendi
1,289513
answered 44 mins ago
berendi
1,289513
1,289513
add a comment |Â
add a comment |Â
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If a bit in the DDR is set for input, the output is floating. The –LORAM, –HIRAM, and –CHAREN lines have a 3.3kΩ pullup to +5V, so they are high in that case.
– Janka
1 hour ago
The real question is if a –RESET clears the DDR and the port register. IIRC no. With certain games, you could switch off the computer, switch it on again a second later and it would not reset correctly, because the ROM was still turned off.
– Janka
1 hour ago
@Janka that's the internal ROM checking a signature at $8000 to see if a cartridge is plugged in, and transferring control to it if the magic value is there. You can fool this detection by having a cartridge signature in RAM, then as long as the memory contents are intact, the ROM reset routine thinks that there is a cartridge plugged in.
– berendi
39 mins ago
Ah, yes, forgot about that. I used it myself once! So the DDR and port are set to 0 on –RESET.
– Janka
13 mins ago
@Janka The actual check at reset looks for the byte sequence
$C3,$C2,$CD,$38,$30at address$8004, and does aJMP ($8000)if present.– berendi
13 mins ago