Verilog - Can you `define a bit slice?

The name of the pictureThe name of the pictureThe name of the pictureClash Royale CLAN TAG#URR8PPP











up vote
2
down vote

favorite












Can you define a bit slice in Verilog?



For example, is this possible:



`define opcode 5:3 // is this possible?

reg [ 7:0 ] a, b;

...

if ( a[ `opcode ] == someValue ) // a[5:3]

 doStuff

if ( b[ `opcode ] == someValue ) // b[5:3]

 doStuff





fpga verilog







share|improve this question



























    up vote
    2
    down vote

    favorite












    Can you define a bit slice in Verilog?



    For example, is this possible:



    `define opcode 5:3 // is this possible?

    reg [ 7:0 ] a, b;

    ...

    if ( a[ `opcode ] == someValue ) // a[5:3]

     doStuff

    if ( b[ `opcode ] == someValue ) // b[5:3]

     doStuff





    fpga verilog







    share|improve this question

























      up vote
      2
      down vote

      favorite









      up vote
      2
      down vote

      favorite











      Can you define a bit slice in Verilog?



      For example, is this possible:



      `define opcode 5:3 // is this possible?

      reg [ 7:0 ] a, b;

      ...

      if ( a[ `opcode ] == someValue ) // a[5:3]

       doStuff

      if ( b[ `opcode ] == someValue ) // b[5:3]

       doStuff





      fpga verilog







      share|improve this question















      Can you define a bit slice in Verilog?



      For example, is this possible:



      `define opcode 5:3 // is this possible?

      reg [ 7:0 ] a, b;

      ...

      if ( a[ `opcode ] == someValue ) // a[5:3]

       doStuff

      if ( b[ `opcode ] == someValue ) // b[5:3]

       doStuff





      fpga verilog




      fpga verilog






      share|improve this question















      share|improve this question













      share|improve this question




      share|improve this question








      edited 5 hours ago

























      asked 7 hours ago









      Jet Blue

      459314




      459314




















          2 Answers
          2






          active

          oldest

          votes

















          up vote
          3
          down vote



          accepted










          You can `define almost any text you want. You would have to use a[`opcode] with the backtick.



          SystemVerilog gives you some other options.



          The let construct declares a name for an expression.



          let opcode = a[5:3];
          ...
          if (opcode==someValue)


          You can use a packed struct.



          struct packed 
           logic [1:0] field1;
           logic [2:0] opcode;
           logic [2:0] field2;
           a;


          Now you can refer to a.opcode as the same as a[5:3].






          share|improve this answer






















          • shouldn't it be logic [5:3] opcode;? - Ah wait, no, it's packed. of course. I presume that order of definition matters. - Is there another kind of struct for doing what I just said? some absolute addressing?
            – Harry Svensson
            5 hours ago











          • Ah oops, added the backticks
            – Jet Blue
            5 hours ago

















          up vote
          0
          down vote













          Yes, you can.



          But it's probably cleaner and easier to simply break the register into fields using wires:



          wire [2:0] a_opcode = a[5:3];

          if (a_opcode == someValue) ...


          How many different registers are you going to be extracting opcodes from?






          share|improve this answer






















          • Note that this solution only works for reading a_opcode, not writing to it. Most of the time, that is OK.
            – dave_59
            6 hours ago










          Your Answer




          StackExchange.ifUsing("editor", function ()
          return StackExchange.using("mathjaxEditing", function ()
          StackExchange.MarkdownEditor.creationCallbacks.add(function (editor, postfix)
          StackExchange.mathjaxEditing.prepareWmdForMathJax(editor, postfix, [["\$", "\$"]]);
          );
          );
          , "mathjax-editing");

          StackExchange.ifUsing("editor", function ()
          return StackExchange.using("schematics", function ()
          StackExchange.schematics.init();
          );
          , "cicuitlab");

          StackExchange.ready(function()
          var channelOptions =
          tags: "".split(" "),
          id: "135"
          ;
          initTagRenderer("".split(" "), "".split(" "), channelOptions);

          StackExchange.using("externalEditor", function()
          // Have to fire editor after snippets, if snippets enabled
          if (StackExchange.settings.snippets.snippetsEnabled)
          StackExchange.using("snippets", function()
          createEditor();
          );

          else
          createEditor();

          );

          function createEditor()
          StackExchange.prepareEditor(
          heartbeatType: 'answer',
          convertImagesToLinks: false,
          noModals: false,
          showLowRepImageUploadWarning: true,
          reputationToPostImages: null,
          bindNavPrevention: true,
          postfix: "",
          onDemand: true,
          discardSelector: ".discard-answer"
          ,immediatelyShowMarkdownHelp:true
          );



          );













           

          draft saved


          draft discarded


















          StackExchange.ready(
          function ()
          StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2felectronics.stackexchange.com%2fquestions%2f397648%2fverilog-can-you-define-a-bit-slice%23new-answer', 'question_page');

          );

          Post as a guest

















          2 Answers
          2






          active

          oldest

          votes








          2 Answers
          2






          active

          oldest

          votes









          active

          oldest

          votes






          active

          oldest

          votes








          up vote
          3
          down vote



          accepted










          You can `define almost any text you want. You would have to use a[`opcode] with the backtick.



          SystemVerilog gives you some other options.



          The let construct declares a name for an expression.



          let opcode = a[5:3];
          ...
          if (opcode==someValue)


          You can use a packed struct.



          struct packed 
           logic [1:0] field1;
           logic [2:0] opcode;
           logic [2:0] field2;
           a;


          Now you can refer to a.opcode as the same as a[5:3].






          share|improve this answer






















          • shouldn't it be logic [5:3] opcode;? - Ah wait, no, it's packed. of course. I presume that order of definition matters. - Is there another kind of struct for doing what I just said? some absolute addressing?
            – Harry Svensson
            5 hours ago











          • Ah oops, added the backticks
            – Jet Blue
            5 hours ago














          up vote
          3
          down vote



          accepted










          You can `define almost any text you want. You would have to use a[`opcode] with the backtick.



          SystemVerilog gives you some other options.



          The let construct declares a name for an expression.



          let opcode = a[5:3];
          ...
          if (opcode==someValue)


          You can use a packed struct.



          struct packed 
           logic [1:0] field1;
           logic [2:0] opcode;
           logic [2:0] field2;
           a;


          Now you can refer to a.opcode as the same as a[5:3].






          share|improve this answer






















          • shouldn't it be logic [5:3] opcode;? - Ah wait, no, it's packed. of course. I presume that order of definition matters. - Is there another kind of struct for doing what I just said? some absolute addressing?
            – Harry Svensson
            5 hours ago











          • Ah oops, added the backticks
            – Jet Blue
            5 hours ago












          up vote
          3
          down vote



          accepted







          up vote
          3
          down vote



          accepted






          You can `define almost any text you want. You would have to use a[`opcode] with the backtick.



          SystemVerilog gives you some other options.



          The let construct declares a name for an expression.



          let opcode = a[5:3];
          ...
          if (opcode==someValue)


          You can use a packed struct.



          struct packed 
           logic [1:0] field1;
           logic [2:0] opcode;
           logic [2:0] field2;
           a;


          Now you can refer to a.opcode as the same as a[5:3].






          share|improve this answer














          You can `define almost any text you want. You would have to use a[`opcode] with the backtick.



          SystemVerilog gives you some other options.



          The let construct declares a name for an expression.



          let opcode = a[5:3];
          ...
          if (opcode==someValue)


          You can use a packed struct.



          struct packed 
           logic [1:0] field1;
           logic [2:0] opcode;
           logic [2:0] field2;
           a;


          Now you can refer to a.opcode as the same as a[5:3].







          share|improve this answer














          share|improve this answer



          share|improve this answer








          edited 21 mins ago









          Dave Tweed♦

          109k9132236




          109k9132236










          answered 6 hours ago









          dave_59

          1,598614




          1,598614











          • shouldn't it be logic [5:3] opcode;? - Ah wait, no, it's packed. of course. I presume that order of definition matters. - Is there another kind of struct for doing what I just said? some absolute addressing?
            – Harry Svensson
            5 hours ago











          • Ah oops, added the backticks
            – Jet Blue
            5 hours ago
















          • shouldn't it be logic [5:3] opcode;? - Ah wait, no, it's packed. of course. I presume that order of definition matters. - Is there another kind of struct for doing what I just said? some absolute addressing?
            – Harry Svensson
            5 hours ago











          • Ah oops, added the backticks
            – Jet Blue
            5 hours ago















          shouldn't it be logic [5:3] opcode;? - Ah wait, no, it's packed. of course. I presume that order of definition matters. - Is there another kind of struct for doing what I just said? some absolute addressing?
          – Harry Svensson
          5 hours ago





          shouldn't it be logic [5:3] opcode;? - Ah wait, no, it's packed. of course. I presume that order of definition matters. - Is there another kind of struct for doing what I just said? some absolute addressing?
          – Harry Svensson
          5 hours ago













          Ah oops, added the backticks
          – Jet Blue
          5 hours ago




          Ah oops, added the backticks
          – Jet Blue
          5 hours ago












          up vote
          0
          down vote













          Yes, you can.



          But it's probably cleaner and easier to simply break the register into fields using wires:



          wire [2:0] a_opcode = a[5:3];

          if (a_opcode == someValue) ...


          How many different registers are you going to be extracting opcodes from?






          share|improve this answer






















          • Note that this solution only works for reading a_opcode, not writing to it. Most of the time, that is OK.
            – dave_59
            6 hours ago














          up vote
          0
          down vote













          Yes, you can.



          But it's probably cleaner and easier to simply break the register into fields using wires:



          wire [2:0] a_opcode = a[5:3];

          if (a_opcode == someValue) ...


          How many different registers are you going to be extracting opcodes from?






          share|improve this answer






















          • Note that this solution only works for reading a_opcode, not writing to it. Most of the time, that is OK.
            – dave_59
            6 hours ago












          up vote
          0
          down vote










          up vote
          0
          down vote









          Yes, you can.



          But it's probably cleaner and easier to simply break the register into fields using wires:



          wire [2:0] a_opcode = a[5:3];

          if (a_opcode == someValue) ...


          How many different registers are you going to be extracting opcodes from?






          share|improve this answer














          Yes, you can.



          But it's probably cleaner and easier to simply break the register into fields using wires:



          wire [2:0] a_opcode = a[5:3];

          if (a_opcode == someValue) ...


          How many different registers are you going to be extracting opcodes from?







          share|improve this answer














          share|improve this answer



          share|improve this answer








          edited 20 mins ago

























          answered 7 hours ago









          Dave Tweed♦

          109k9132236




          109k9132236











          • Note that this solution only works for reading a_opcode, not writing to it. Most of the time, that is OK.
            – dave_59
            6 hours ago
















          • Note that this solution only works for reading a_opcode, not writing to it. Most of the time, that is OK.
            – dave_59
            6 hours ago















          Note that this solution only works for reading a_opcode, not writing to it. Most of the time, that is OK.
          – dave_59
          6 hours ago




          Note that this solution only works for reading a_opcode, not writing to it. Most of the time, that is OK.
          – dave_59
          6 hours ago

















           

          draft saved


          draft discarded















































           


          draft saved


          draft discarded














          StackExchange.ready(
          function ()
          StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2felectronics.stackexchange.com%2fquestions%2f397648%2fverilog-can-you-define-a-bit-slice%23new-answer', 'question_page');

          );

          Post as a guest
































































          Comments

          Post a Comment

          Popular posts from this blog

          What does second last employer means? [closed]

          Image
          Clash Royale CLAN TAG #URR8PPP .everyoneloves__top-leaderboard:empty,.everyoneloves__mid-leaderboard:empty margin-bottom:0; up vote -3 down vote favorite Say, for example I have worked in the following companies, Company A => 2010 - 2011 Company B => 2011 - 2012 Company C => 2012 - Till Date Company D => Have offer Now assume Company D is asking to submit documents from my second last employer. So from the list of companies given, which company would be qualified as second last employer? software-industry employer share | improve this question asked Aug 10 '14 at 5:16 Rajaprabhu Aravindasamy 559 1 6 13 closed as off-topic by Jim G., jmort253 ♦ Aug 11 '14 at 1:58 This question appears to be off-topic. The users who voted to close gave this specific reason: "Questions seeking advice on company-specific regulations, agreements, or policies should be directed to your manager or HR department. Questions that address...
          Read more

          List of Gilmore Girls characters

          Image
          The season three cast—(Back row): Lane, Michel, Paris, Emily, Richard, Sookie, Miss Patty, Kirk; Front row: Jess, Luke, Lorelai, Rory, Dean This is a list of characters for the comedy-drama television series Gilmore Girls . Contents 1 Main characters 1.1 Lorelai Gilmore 1.2 Rory Gilmore 1.3 Sookie St. James 1.4 Lane Kim 1.5 Michel Gerard 1.6 Luke Danes 1.7 Emily Gilmore 1.8 Richard Gilmore 1.9 Paris Geller 1.10 Dean Forester 1.11 Jess Mariano 1.12 Kirk Gleason 1.13 Jason Stiles 1.14 Logan Huntzberger 2 Major recurring characters 2.1 Christopher Hayden 2.2 Jackson Belleville 2.3 Mrs. Kim 2.4 Tristin DuGray 2.5 Max Medina 2.6 Taylor Doose 2.7 Dave Rygalski 2.8 Marty 3 Recurring characters 3.1 Stars Hollow 3.2 Chilton 3.3 Yale 3.4 Other 4 Notable guest stars 5 Unseen characters 6 Notes 7 References Main characters Actor Character Appearances Season 1 Season 2 Season 3 Season 4 Season 5 Season 6 Season 7 A Year in the Life Lauren Graham Lorelai Gilmore...
          Read more

          Confectionery

          Image
          Prepared foods made with a lot of sugar or other cabohydrates "Sweetmeat" redirects here. For the racehorse, see Sweetmeat (horse). Not to be confused with Sweetbread. This Kransekake is a traditional Scandinavian baker's confection. Confectionery is the art of making confections , which are food items that are rich in sugar and carbohydrates. Exact definitions are difficult. [1] In general, though, confectionery is divided into two broad and somewhat overlapping categories, bakers' confections and sugar confections. [2] Bakers' confectionery, also called flour confections , includes principally sweet pastries, cakes, and similar baked goods. Sugar confectionery includes candies ( sweets in British English), candied nuts, chocolates, chewing gum, bubble gum, pastillage, and other confections that are made primarily of sugar. In some cases, chocolate confections (confections made of chocolate) are treated as a separate category, as are sugar-free versions of ...
          Read more