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Why are the SRAM data and address pins numbered?
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As far as understand, it would make no difference to the operation of an SRAM if you mixed up the order of the address or data pins.
E.g. http://www.farnell.com/datasheets/1911297.pdf?_ga=2.220805788.545458806.1537605448-1970519925.1482350159
Removable non-volatile chips, such as PROMs and EEPROMs, have address and data pin numberings defined, as they need to be consistent across programmers and application circuits.
Why do SRAM chips have numbered data and address pins?
Is there any operation impact if I swap address pins around to make a PCB easier to route?
sram addressing homebrew-cpu
asked 28 mins ago
fadedbee
468214
add a comment |Â
up vote
5
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As far as understand, it would make no difference to the operation of an SRAM if you mixed up the order of the address or data pins.
E.g. http://www.farnell.com/datasheets/1911297.pdf?_ga=2.220805788.545458806.1537605448-1970519925.1482350159
Removable non-volatile chips, such as PROMs and EEPROMs, have address and data pin numberings defined, as they need to be consistent across programmers and application circuits.
Why do SRAM chips have numbered data and address pins?
Is there any operation impact if I swap address pins around to make a PCB easier to route?
sram addressing homebrew-cpu
asked 28 mins ago
fadedbee
468214
add a comment |Â
up vote
5
down vote
favorite
up vote
5
down vote
favorite
As far as understand, it would make no difference to the operation of an SRAM if you mixed up the order of the address or data pins.
E.g. http://www.farnell.com/datasheets/1911297.pdf?_ga=2.220805788.545458806.1537605448-1970519925.1482350159
Removable non-volatile chips, such as PROMs and EEPROMs, have address and data pin numberings defined, as they need to be consistent across programmers and application circuits.
Why do SRAM chips have numbered data and address pins?
Is there any operation impact if I swap address pins around to make a PCB easier to route?
sram addressing homebrew-cpu
asked 28 mins ago
fadedbee
468214
As far as understand, it would make no difference to the operation of an SRAM if you mixed up the order of the address or data pins.
E.g. http://www.farnell.com/datasheets/1911297.pdf?_ga=2.220805788.545458806.1537605448-1970519925.1482350159
Removable non-volatile chips, such as PROMs and EEPROMs, have address and data pin numberings defined, as they need to be consistent across programmers and application circuits.
Why do SRAM chips have numbered data and address pins?
Is there any operation impact if I swap address pins around to make a PCB easier to route?
sram addressing homebrew-cpu
sram addressing homebrew-cpu
asked 28 mins ago
fadedbee
468214
asked 28 mins ago
fadedbee
468214
asked 28 mins ago
fadedbee
468214
asked 28 mins ago
fadedbee
468214
asked 28 mins ago
fadedbee
468214
468214
add a comment |Â
add a comment |Â
2 Answers
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You are quite correct. With an SRAM, where all address pins are equivalent, you can indeed juggle the address pins around within their set on your board to ease layout, and also for the data pins. I would strongly advise putting a note on the board that you've done this, to avoid freaking out any subsequent engineer who comes along to debug or modify it.
Why are they labelled? If the pin functions were labelled 'pool of address pins' and 'pool of data pins', then at some point your CAD tool would insist on identifying them, and you would need to make a choice, even if it was only 'ADR_line_pin_23' sort of identifiers. So they do it for you. It's convenient, and recognisable, each pin has a physical identifier and a function identifier.
When the manufacturer does it, and is consistent with standards like JEDEC, it eases the task of engineers debugging stuff. If I've learned the pinout of a particular package style, then I can expect to find those signals on the same pins without an extra translation step through the schematic, the less mental work I have to do when debugging, the better. 'Let's see, this is word addressable, so the LSB adress shouldn't be changing at all as it reads memory, now where is the LSB'.
Exactly the same goes for multiple functions in a single package. While a quad opamp in a single package tends not to be labelled amp0, amp1 etc, a triple analogue switch does tend to be labelled s0, s1 and s2.
answered 17 mins ago
Neil_UK
70.2k273155
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up vote
3
down vote
Some reasons :
Pinouts are often standardized between static RAM and EPROM/FLASH: "JEDEC"
RAMs are usually arranged in matrices with lines and columns. Using consecutive addresses may require a little bit less power. For events that affect the matrix, such as hardware defects or a SEU (high energy particle hitting atoms), knowing which memory cells are adjacent may be useful for finding errors or designing error correction codes.
Yes, you can swap address and data pins on static RAM.
answered 16 mins ago
TEMLIB
1,7571713
The standardisation isn't good - the 4Mbit SRAM AS6C4008 and the 4Mbit EPROM AT27C040 have A15, A14 and A18 on different pins.
– fadedbee
8 mins ago
add a comment |Â
2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
up vote
4
down vote
You are quite correct. With an SRAM, where all address pins are equivalent, you can indeed juggle the address pins around within their set on your board to ease layout, and also for the data pins. I would strongly advise putting a note on the board that you've done this, to avoid freaking out any subsequent engineer who comes along to debug or modify it.
Why are they labelled? If the pin functions were labelled 'pool of address pins' and 'pool of data pins', then at some point your CAD tool would insist on identifying them, and you would need to make a choice, even if it was only 'ADR_line_pin_23' sort of identifiers. So they do it for you. It's convenient, and recognisable, each pin has a physical identifier and a function identifier.
When the manufacturer does it, and is consistent with standards like JEDEC, it eases the task of engineers debugging stuff. If I've learned the pinout of a particular package style, then I can expect to find those signals on the same pins without an extra translation step through the schematic, the less mental work I have to do when debugging, the better. 'Let's see, this is word addressable, so the LSB adress shouldn't be changing at all as it reads memory, now where is the LSB'.
Exactly the same goes for multiple functions in a single package. While a quad opamp in a single package tends not to be labelled amp0, amp1 etc, a triple analogue switch does tend to be labelled s0, s1 and s2.
answered 17 mins ago
Neil_UK
70.2k273155
add a comment |Â
up vote
4
down vote
You are quite correct. With an SRAM, where all address pins are equivalent, you can indeed juggle the address pins around within their set on your board to ease layout, and also for the data pins. I would strongly advise putting a note on the board that you've done this, to avoid freaking out any subsequent engineer who comes along to debug or modify it.
Why are they labelled? If the pin functions were labelled 'pool of address pins' and 'pool of data pins', then at some point your CAD tool would insist on identifying them, and you would need to make a choice, even if it was only 'ADR_line_pin_23' sort of identifiers. So they do it for you. It's convenient, and recognisable, each pin has a physical identifier and a function identifier.
When the manufacturer does it, and is consistent with standards like JEDEC, it eases the task of engineers debugging stuff. If I've learned the pinout of a particular package style, then I can expect to find those signals on the same pins without an extra translation step through the schematic, the less mental work I have to do when debugging, the better. 'Let's see, this is word addressable, so the LSB adress shouldn't be changing at all as it reads memory, now where is the LSB'.
Exactly the same goes for multiple functions in a single package. While a quad opamp in a single package tends not to be labelled amp0, amp1 etc, a triple analogue switch does tend to be labelled s0, s1 and s2.
answered 17 mins ago
Neil_UK
70.2k273155
add a comment |Â
up vote
4
down vote
up vote
4
down vote
You are quite correct. With an SRAM, where all address pins are equivalent, you can indeed juggle the address pins around within their set on your board to ease layout, and also for the data pins. I would strongly advise putting a note on the board that you've done this, to avoid freaking out any subsequent engineer who comes along to debug or modify it.
Why are they labelled? If the pin functions were labelled 'pool of address pins' and 'pool of data pins', then at some point your CAD tool would insist on identifying them, and you would need to make a choice, even if it was only 'ADR_line_pin_23' sort of identifiers. So they do it for you. It's convenient, and recognisable, each pin has a physical identifier and a function identifier.
When the manufacturer does it, and is consistent with standards like JEDEC, it eases the task of engineers debugging stuff. If I've learned the pinout of a particular package style, then I can expect to find those signals on the same pins without an extra translation step through the schematic, the less mental work I have to do when debugging, the better. 'Let's see, this is word addressable, so the LSB adress shouldn't be changing at all as it reads memory, now where is the LSB'.
Exactly the same goes for multiple functions in a single package. While a quad opamp in a single package tends not to be labelled amp0, amp1 etc, a triple analogue switch does tend to be labelled s0, s1 and s2.
answered 17 mins ago
Neil_UK
70.2k273155
You are quite correct. With an SRAM, where all address pins are equivalent, you can indeed juggle the address pins around within their set on your board to ease layout, and also for the data pins. I would strongly advise putting a note on the board that you've done this, to avoid freaking out any subsequent engineer who comes along to debug or modify it.
Why are they labelled? If the pin functions were labelled 'pool of address pins' and 'pool of data pins', then at some point your CAD tool would insist on identifying them, and you would need to make a choice, even if it was only 'ADR_line_pin_23' sort of identifiers. So they do it for you. It's convenient, and recognisable, each pin has a physical identifier and a function identifier.
When the manufacturer does it, and is consistent with standards like JEDEC, it eases the task of engineers debugging stuff. If I've learned the pinout of a particular package style, then I can expect to find those signals on the same pins without an extra translation step through the schematic, the less mental work I have to do when debugging, the better. 'Let's see, this is word addressable, so the LSB adress shouldn't be changing at all as it reads memory, now where is the LSB'.
Exactly the same goes for multiple functions in a single package. While a quad opamp in a single package tends not to be labelled amp0, amp1 etc, a triple analogue switch does tend to be labelled s0, s1 and s2.
answered 17 mins ago
Neil_UK
70.2k273155
edited 11 mins ago
answered 17 mins ago
Neil_UK
70.2k273155
answered 17 mins ago
Neil_UK
70.2k273155
answered 17 mins ago
Neil_UK
70.2k273155
70.2k273155
add a comment |Â
add a comment |Â
up vote
3
down vote
Some reasons :
Pinouts are often standardized between static RAM and EPROM/FLASH: "JEDEC"
RAMs are usually arranged in matrices with lines and columns. Using consecutive addresses may require a little bit less power. For events that affect the matrix, such as hardware defects or a SEU (high energy particle hitting atoms), knowing which memory cells are adjacent may be useful for finding errors or designing error correction codes.
Yes, you can swap address and data pins on static RAM.
answered 16 mins ago
TEMLIB
1,7571713
The standardisation isn't good - the 4Mbit SRAM AS6C4008 and the 4Mbit EPROM AT27C040 have A15, A14 and A18 on different pins.
– fadedbee
8 mins ago
add a comment |Â
up vote
3
down vote
Some reasons :
Pinouts are often standardized between static RAM and EPROM/FLASH: "JEDEC"
RAMs are usually arranged in matrices with lines and columns. Using consecutive addresses may require a little bit less power. For events that affect the matrix, such as hardware defects or a SEU (high energy particle hitting atoms), knowing which memory cells are adjacent may be useful for finding errors or designing error correction codes.
Yes, you can swap address and data pins on static RAM.
answered 16 mins ago
TEMLIB
1,7571713
The standardisation isn't good - the 4Mbit SRAM AS6C4008 and the 4Mbit EPROM AT27C040 have A15, A14 and A18 on different pins.
– fadedbee
8 mins ago
add a comment |Â
up vote
3
down vote
up vote
3
down vote
Some reasons :
Pinouts are often standardized between static RAM and EPROM/FLASH: "JEDEC"
RAMs are usually arranged in matrices with lines and columns. Using consecutive addresses may require a little bit less power. For events that affect the matrix, such as hardware defects or a SEU (high energy particle hitting atoms), knowing which memory cells are adjacent may be useful for finding errors or designing error correction codes.
Yes, you can swap address and data pins on static RAM.
answered 16 mins ago
TEMLIB
1,7571713
Some reasons :
Pinouts are often standardized between static RAM and EPROM/FLASH: "JEDEC"
RAMs are usually arranged in matrices with lines and columns. Using consecutive addresses may require a little bit less power. For events that affect the matrix, such as hardware defects or a SEU (high energy particle hitting atoms), knowing which memory cells are adjacent may be useful for finding errors or designing error correction codes.
Yes, you can swap address and data pins on static RAM.
answered 16 mins ago
TEMLIB
1,7571713
answered 16 mins ago
TEMLIB
1,7571713
answered 16 mins ago
TEMLIB
1,7571713
answered 16 mins ago
TEMLIB
1,7571713
1,7571713
The standardisation isn't good - the 4Mbit SRAM AS6C4008 and the 4Mbit EPROM AT27C040 have A15, A14 and A18 on different pins.
– fadedbee
8 mins ago
add a comment |Â
The standardisation isn't good - the 4Mbit SRAM AS6C4008 and the 4Mbit EPROM AT27C040 have A15, A14 and A18 on different pins.
– fadedbee
8 mins ago
The standardisation isn't good - the 4Mbit SRAM AS6C4008 and the 4Mbit EPROM AT27C040 have A15, A14 and A18 on different pins.
– fadedbee
8 mins ago
The standardisation isn't good - the 4Mbit SRAM AS6C4008 and the 4Mbit EPROM AT27C040 have A15, A14 and A18 on different pins.
– fadedbee
8 mins ago
add a comment |Â
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