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Instruction set support for multiplication with a constant
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Before integer multipliers in silicon, several cpus had some support for multiplication. For instance SPARCv7 has the MULScc multiply-step instruction (several other cpus also have this).
As far as I know, PA-RISC computers before PA-7100 (probably) had no hardware for integer multiplication, but support for multiplication with a constant was enhanced beyond the usual shift and add instructions. Multiplication by a constant could be given by a sequence of instructions add, sub, sl, sh1add, sh2add, sh3add, neg and shl, see https://patents.google.com/patent/US5764990A/en
Were there other cpus, earlier or later, that used the strategy of PA-RISC (sh1add, sh2add, sh3add)?
instruction-set hp cpu
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Baard
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up vote
3
down vote
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Before integer multipliers in silicon, several cpus had some support for multiplication. For instance SPARCv7 has the MULScc multiply-step instruction (several other cpus also have this).
As far as I know, PA-RISC computers before PA-7100 (probably) had no hardware for integer multiplication, but support for multiplication with a constant was enhanced beyond the usual shift and add instructions. Multiplication by a constant could be given by a sequence of instructions add, sub, sl, sh1add, sh2add, sh3add, neg and shl, see https://patents.google.com/patent/US5764990A/en
Were there other cpus, earlier or later, that used the strategy of PA-RISC (sh1add, sh2add, sh3add)?
instruction-set hp cpu
asked 4 hours ago
Baard
1785
New contributor
Baard is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
1
Interesting they actually got a patent for that. This method has been around for decades before 1996 (Obviously not directly in the ALU, but by the appropriate series of separate instructions). And even if your CPU has multiply, shift+add might still be faster for some values than a generic multiplication
– tofro
3 hours ago
2
Interestingly this(x<<a)+ykind of instructions has a lot of usage in address generation and pointer arithmetic, e.g. to incrementypointer byxintegers.
– user3528438
3 hours ago
It's unclear to me whether combining shift and add into a single instruction really counts as "instruction set support" for multiplication by a constant. On the surface the sh1add, sh2add and sh3add instructions appear to be shortened opcodes that allow the address of 2-byte, 4-byte and 8-byte array entries to be computed in one step. The ability to leverage these array-lookup opcodes to multiply by arbitrary constants appears to be more of a compiler innovation than an instruction set one, and the patent is very clear that it is a method for compilers to use.
– Ken Gober
3 hours ago
1
Isn’t that similar to the common x86 technique usingLEA?
– Stephen Kitt
3 hours ago
@KenGober, there are more to the sh<x>add instructions than my abbreviated description. Yes, the patent deals with the way to store sequences, hence a compiler invention, but the underlying hardware enables such sequences in the first place.
– Baard
3 hours ago
 |Â
show 1 more comment
up vote
3
down vote
favorite
up vote
3
down vote
favorite
Before integer multipliers in silicon, several cpus had some support for multiplication. For instance SPARCv7 has the MULScc multiply-step instruction (several other cpus also have this).
As far as I know, PA-RISC computers before PA-7100 (probably) had no hardware for integer multiplication, but support for multiplication with a constant was enhanced beyond the usual shift and add instructions. Multiplication by a constant could be given by a sequence of instructions add, sub, sl, sh1add, sh2add, sh3add, neg and shl, see https://patents.google.com/patent/US5764990A/en
Were there other cpus, earlier or later, that used the strategy of PA-RISC (sh1add, sh2add, sh3add)?
instruction-set hp cpu
asked 4 hours ago
Baard
1785
New contributor
Baard is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
Before integer multipliers in silicon, several cpus had some support for multiplication. For instance SPARCv7 has the MULScc multiply-step instruction (several other cpus also have this).
As far as I know, PA-RISC computers before PA-7100 (probably) had no hardware for integer multiplication, but support for multiplication with a constant was enhanced beyond the usual shift and add instructions. Multiplication by a constant could be given by a sequence of instructions add, sub, sl, sh1add, sh2add, sh3add, neg and shl, see https://patents.google.com/patent/US5764990A/en
Were there other cpus, earlier or later, that used the strategy of PA-RISC (sh1add, sh2add, sh3add)?
instruction-set hp cpu
instruction-set hp cpu
asked 4 hours ago
Baard
1785
New contributor
Baard is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 4 hours ago
Baard
1785
New contributor
Baard is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
edited 3 hours ago
asked 4 hours ago
Baard
1785
New contributor
Baard is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
asked 4 hours ago
Baard
1785
asked 4 hours ago
Baard
1785
1785
New contributor
Baard is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
New contributor
Baard is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
Baard is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.
1
Interesting they actually got a patent for that. This method has been around for decades before 1996 (Obviously not directly in the ALU, but by the appropriate series of separate instructions). And even if your CPU has multiply, shift+add might still be faster for some values than a generic multiplication
– tofro
3 hours ago
2
Interestingly this(x<<a)+ykind of instructions has a lot of usage in address generation and pointer arithmetic, e.g. to incrementypointer byxintegers.
– user3528438
3 hours ago
It's unclear to me whether combining shift and add into a single instruction really counts as "instruction set support" for multiplication by a constant. On the surface the sh1add, sh2add and sh3add instructions appear to be shortened opcodes that allow the address of 2-byte, 4-byte and 8-byte array entries to be computed in one step. The ability to leverage these array-lookup opcodes to multiply by arbitrary constants appears to be more of a compiler innovation than an instruction set one, and the patent is very clear that it is a method for compilers to use.
– Ken Gober
3 hours ago
1
Isn’t that similar to the common x86 technique usingLEA?
– Stephen Kitt
3 hours ago
@KenGober, there are more to the sh<x>add instructions than my abbreviated description. Yes, the patent deals with the way to store sequences, hence a compiler invention, but the underlying hardware enables such sequences in the first place.
– Baard
3 hours ago
 |Â
show 1 more comment
1
Interesting they actually got a patent for that. This method has been around for decades before 1996 (Obviously not directly in the ALU, but by the appropriate series of separate instructions). And even if your CPU has multiply, shift+add might still be faster for some values than a generic multiplication
– tofro
3 hours ago
2
Interestingly this(x<<a)+ykind of instructions has a lot of usage in address generation and pointer arithmetic, e.g. to incrementypointer byxintegers.
– user3528438
3 hours ago
It's unclear to me whether combining shift and add into a single instruction really counts as "instruction set support" for multiplication by a constant. On the surface the sh1add, sh2add and sh3add instructions appear to be shortened opcodes that allow the address of 2-byte, 4-byte and 8-byte array entries to be computed in one step. The ability to leverage these array-lookup opcodes to multiply by arbitrary constants appears to be more of a compiler innovation than an instruction set one, and the patent is very clear that it is a method for compilers to use.
– Ken Gober
3 hours ago
1
Isn’t that similar to the common x86 technique usingLEA?
– Stephen Kitt
3 hours ago
@KenGober, there are more to the sh<x>add instructions than my abbreviated description. Yes, the patent deals with the way to store sequences, hence a compiler invention, but the underlying hardware enables such sequences in the first place.
– Baard
3 hours ago
1
1
Interesting they actually got a patent for that. This method has been around for decades before 1996 (Obviously not directly in the ALU, but by the appropriate series of separate instructions). And even if your CPU has multiply, shift+add might still be faster for some values than a generic multiplication
– tofro
3 hours ago
Interesting they actually got a patent for that. This method has been around for decades before 1996 (Obviously not directly in the ALU, but by the appropriate series of separate instructions). And even if your CPU has multiply, shift+add might still be faster for some values than a generic multiplication
– tofro
3 hours ago
2
2
Interestingly this
(x<<a)+y kind of instructions has a lot of usage in address generation and pointer arithmetic, e.g. to increment y pointer by x integers.– user3528438
3 hours ago
Interestingly this
(x<<a)+y kind of instructions has a lot of usage in address generation and pointer arithmetic, e.g. to increment y pointer by x integers.– user3528438
3 hours ago
It's unclear to me whether combining shift and add into a single instruction really counts as "instruction set support" for multiplication by a constant. On the surface the sh1add, sh2add and sh3add instructions appear to be shortened opcodes that allow the address of 2-byte, 4-byte and 8-byte array entries to be computed in one step. The ability to leverage these array-lookup opcodes to multiply by arbitrary constants appears to be more of a compiler innovation than an instruction set one, and the patent is very clear that it is a method for compilers to use.
– Ken Gober
3 hours ago
It's unclear to me whether combining shift and add into a single instruction really counts as "instruction set support" for multiplication by a constant. On the surface the sh1add, sh2add and sh3add instructions appear to be shortened opcodes that allow the address of 2-byte, 4-byte and 8-byte array entries to be computed in one step. The ability to leverage these array-lookup opcodes to multiply by arbitrary constants appears to be more of a compiler innovation than an instruction set one, and the patent is very clear that it is a method for compilers to use.
– Ken Gober
3 hours ago
1
1
Isn’t that similar to the common x86 technique using
LEA?– Stephen Kitt
3 hours ago
Isn’t that similar to the common x86 technique using
LEA?– Stephen Kitt
3 hours ago
@KenGober, there are more to the sh<x>add instructions than my abbreviated description. Yes, the patent deals with the way to store sequences, hence a compiler invention, but the underlying hardware enables such sequences in the first place.
– Baard
3 hours ago
@KenGober, there are more to the sh<x>add instructions than my abbreviated description. Yes, the patent deals with the way to store sequences, hence a compiler invention, but the underlying hardware enables such sequences in the first place.
– Baard
3 hours ago
 |Â
show 1 more comment
2 Answers
2
active
oldest
votes
up vote
2
down vote
accepted
In the original ARM instruction set, there are no dedicated shift and roll instructions; instead the second operand of each instruction always passes through the barrel shifter, so shifts and rolls are always applied as prefixes to other operations.
You can make the instruction a simple MOV to get the same result as a traditional shift or rotate operation.
Or you could make the instruction an ADD to get the same functionality as any of the listed sh?adds, or equivalents that shift or roll by any other amount in either direction.
I guess in a literal sense that's not the processor seeking to implement the same strategy as PA-RISC, it's a natural outcome of allowing rolls and shifts everywhere, but it gives the programmer the tools necessary to reach exactly the same outcome.
answered 2 hours ago
Tommy
12.6k13264
For completeness, I'd also mention the year of introduction for ARM (1983) and PA-RISC (1986).
– dirkt
10 mins ago
add a comment |Â
up vote
2
down vote
The VAX, sold first in 1977, has a scaled indexed addressing mode, which offers indexReg*constScale+baseReg address computation. When used with an LEA instruction (load effective address), this offers a shift and add.
The 68020 (released 1984) introduced scaled indexed addressing mode, which when accomplishes indexReg*constScale + constOffset + baseReg; the 680x0 series also has LEA.
And one comment mentioned LEA on x86; the 80386, introduced 1985, supports a scaled indexed addressing mode as well.
You noted PA-RISC already, which was first released in 1986.
answered 2 hours ago
Erik Eidt
792310
Scaled indexed addressing modes has often been pressed into service for constant multiplication. The way I stated the question this answer is good. However, the answer of @Tommy below is even better.
– Baard
5 mins ago
add a comment |Â
2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
up vote
2
down vote
accepted
In the original ARM instruction set, there are no dedicated shift and roll instructions; instead the second operand of each instruction always passes through the barrel shifter, so shifts and rolls are always applied as prefixes to other operations.
You can make the instruction a simple MOV to get the same result as a traditional shift or rotate operation.
Or you could make the instruction an ADD to get the same functionality as any of the listed sh?adds, or equivalents that shift or roll by any other amount in either direction.
I guess in a literal sense that's not the processor seeking to implement the same strategy as PA-RISC, it's a natural outcome of allowing rolls and shifts everywhere, but it gives the programmer the tools necessary to reach exactly the same outcome.
answered 2 hours ago
Tommy
12.6k13264
For completeness, I'd also mention the year of introduction for ARM (1983) and PA-RISC (1986).
– dirkt
10 mins ago
add a comment |Â
up vote
2
down vote
accepted
In the original ARM instruction set, there are no dedicated shift and roll instructions; instead the second operand of each instruction always passes through the barrel shifter, so shifts and rolls are always applied as prefixes to other operations.
You can make the instruction a simple MOV to get the same result as a traditional shift or rotate operation.
Or you could make the instruction an ADD to get the same functionality as any of the listed sh?adds, or equivalents that shift or roll by any other amount in either direction.
I guess in a literal sense that's not the processor seeking to implement the same strategy as PA-RISC, it's a natural outcome of allowing rolls and shifts everywhere, but it gives the programmer the tools necessary to reach exactly the same outcome.
answered 2 hours ago
Tommy
12.6k13264
For completeness, I'd also mention the year of introduction for ARM (1983) and PA-RISC (1986).
– dirkt
10 mins ago
add a comment |Â
up vote
2
down vote
accepted
up vote
2
down vote
accepted
In the original ARM instruction set, there are no dedicated shift and roll instructions; instead the second operand of each instruction always passes through the barrel shifter, so shifts and rolls are always applied as prefixes to other operations.
You can make the instruction a simple MOV to get the same result as a traditional shift or rotate operation.
Or you could make the instruction an ADD to get the same functionality as any of the listed sh?adds, or equivalents that shift or roll by any other amount in either direction.
I guess in a literal sense that's not the processor seeking to implement the same strategy as PA-RISC, it's a natural outcome of allowing rolls and shifts everywhere, but it gives the programmer the tools necessary to reach exactly the same outcome.
answered 2 hours ago
Tommy
12.6k13264
In the original ARM instruction set, there are no dedicated shift and roll instructions; instead the second operand of each instruction always passes through the barrel shifter, so shifts and rolls are always applied as prefixes to other operations.
You can make the instruction a simple MOV to get the same result as a traditional shift or rotate operation.
Or you could make the instruction an ADD to get the same functionality as any of the listed sh?adds, or equivalents that shift or roll by any other amount in either direction.
I guess in a literal sense that's not the processor seeking to implement the same strategy as PA-RISC, it's a natural outcome of allowing rolls and shifts everywhere, but it gives the programmer the tools necessary to reach exactly the same outcome.
answered 2 hours ago
Tommy
12.6k13264
answered 2 hours ago
Tommy
12.6k13264
answered 2 hours ago
Tommy
12.6k13264
answered 2 hours ago
Tommy
12.6k13264
12.6k13264
For completeness, I'd also mention the year of introduction for ARM (1983) and PA-RISC (1986).
– dirkt
10 mins ago
add a comment |Â
For completeness, I'd also mention the year of introduction for ARM (1983) and PA-RISC (1986).
– dirkt
10 mins ago
For completeness, I'd also mention the year of introduction for ARM (1983) and PA-RISC (1986).
– dirkt
10 mins ago
For completeness, I'd also mention the year of introduction for ARM (1983) and PA-RISC (1986).
– dirkt
10 mins ago
add a comment |Â
up vote
2
down vote
The VAX, sold first in 1977, has a scaled indexed addressing mode, which offers indexReg*constScale+baseReg address computation. When used with an LEA instruction (load effective address), this offers a shift and add.
The 68020 (released 1984) introduced scaled indexed addressing mode, which when accomplishes indexReg*constScale + constOffset + baseReg; the 680x0 series also has LEA.
And one comment mentioned LEA on x86; the 80386, introduced 1985, supports a scaled indexed addressing mode as well.
You noted PA-RISC already, which was first released in 1986.
answered 2 hours ago
Erik Eidt
792310
Scaled indexed addressing modes has often been pressed into service for constant multiplication. The way I stated the question this answer is good. However, the answer of @Tommy below is even better.
– Baard
5 mins ago
add a comment |Â
up vote
2
down vote
The VAX, sold first in 1977, has a scaled indexed addressing mode, which offers indexReg*constScale+baseReg address computation. When used with an LEA instruction (load effective address), this offers a shift and add.
The 68020 (released 1984) introduced scaled indexed addressing mode, which when accomplishes indexReg*constScale + constOffset + baseReg; the 680x0 series also has LEA.
And one comment mentioned LEA on x86; the 80386, introduced 1985, supports a scaled indexed addressing mode as well.
You noted PA-RISC already, which was first released in 1986.
answered 2 hours ago
Erik Eidt
792310
Scaled indexed addressing modes has often been pressed into service for constant multiplication. The way I stated the question this answer is good. However, the answer of @Tommy below is even better.
– Baard
5 mins ago
add a comment |Â
up vote
2
down vote
up vote
2
down vote
The VAX, sold first in 1977, has a scaled indexed addressing mode, which offers indexReg*constScale+baseReg address computation. When used with an LEA instruction (load effective address), this offers a shift and add.
The 68020 (released 1984) introduced scaled indexed addressing mode, which when accomplishes indexReg*constScale + constOffset + baseReg; the 680x0 series also has LEA.
And one comment mentioned LEA on x86; the 80386, introduced 1985, supports a scaled indexed addressing mode as well.
You noted PA-RISC already, which was first released in 1986.
answered 2 hours ago
Erik Eidt
792310
The VAX, sold first in 1977, has a scaled indexed addressing mode, which offers indexReg*constScale+baseReg address computation. When used with an LEA instruction (load effective address), this offers a shift and add.
The 68020 (released 1984) introduced scaled indexed addressing mode, which when accomplishes indexReg*constScale + constOffset + baseReg; the 680x0 series also has LEA.
And one comment mentioned LEA on x86; the 80386, introduced 1985, supports a scaled indexed addressing mode as well.
You noted PA-RISC already, which was first released in 1986.
answered 2 hours ago
Erik Eidt
792310
answered 2 hours ago
Erik Eidt
792310
answered 2 hours ago
Erik Eidt
792310
answered 2 hours ago
Erik Eidt
792310
792310
Scaled indexed addressing modes has often been pressed into service for constant multiplication. The way I stated the question this answer is good. However, the answer of @Tommy below is even better.
– Baard
5 mins ago
add a comment |Â
Scaled indexed addressing modes has often been pressed into service for constant multiplication. The way I stated the question this answer is good. However, the answer of @Tommy below is even better.
– Baard
5 mins ago
Scaled indexed addressing modes has often been pressed into service for constant multiplication. The way I stated the question this answer is good. However, the answer of @Tommy below is even better.
– Baard
5 mins ago
Scaled indexed addressing modes has often been pressed into service for constant multiplication. The way I stated the question this answer is good. However, the answer of @Tommy below is even better.
– Baard
5 mins ago
add a comment |Â
Baard is a new contributor. Be nice, and check out our Code of Conduct.
Baard is a new contributor. Be nice, and check out our Code of Conduct.
Baard is a new contributor. Be nice, and check out our Code of Conduct.
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1
Interesting they actually got a patent for that. This method has been around for decades before 1996 (Obviously not directly in the ALU, but by the appropriate series of separate instructions). And even if your CPU has multiply, shift+add might still be faster for some values than a generic multiplication
– tofro
3 hours ago
2
Interestingly this
(x<<a)+ykind of instructions has a lot of usage in address generation and pointer arithmetic, e.g. to incrementypointer byxintegers.– user3528438
3 hours ago
It's unclear to me whether combining shift and add into a single instruction really counts as "instruction set support" for multiplication by a constant. On the surface the sh1add, sh2add and sh3add instructions appear to be shortened opcodes that allow the address of 2-byte, 4-byte and 8-byte array entries to be computed in one step. The ability to leverage these array-lookup opcodes to multiply by arbitrary constants appears to be more of a compiler innovation than an instruction set one, and the patent is very clear that it is a method for compilers to use.
– Ken Gober
3 hours ago
1
Isn’t that similar to the common x86 technique using
LEA?– Stephen Kitt
3 hours ago
@KenGober, there are more to the sh<x>add instructions than my abbreviated description. Yes, the patent deals with the way to store sequences, hence a compiler invention, but the underlying hardware enables such sequences in the first place.
– Baard
3 hours ago