Z80 16-bit IO port addresses

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The Z80 indirect I/O instructions are a little quirky: the instructions with the standard mnemonic in r, (c) (where r is a stand-in for any of the normal registers) actually puts the register pair bc on the address bus, not just c as implied in the mnemonic, and likewise for out (c), r. This capability is rarely used, but there are some instances (e.g. the keyboards of the ZX81 and Spectrum use the upper byte to select a row to scan) where it was used to good effect.



Is this behaviour intentional, in order to allow the Z80 to expand beyond the 256 port limit of the 8080 -- in which case, is the reason it wasn't documented known? -- or is it a result of a bug in the processor implementation (presumably a microcode error that wasn't detected prior to release)?






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    The Z80 indirect I/O instructions are a little quirky: the instructions with the standard mnemonic in r, (c) (where r is a stand-in for any of the normal registers) actually puts the register pair bc on the address bus, not just c as implied in the mnemonic, and likewise for out (c), r. This capability is rarely used, but there are some instances (e.g. the keyboards of the ZX81 and Spectrum use the upper byte to select a row to scan) where it was used to good effect.



    Is this behaviour intentional, in order to allow the Z80 to expand beyond the 256 port limit of the 8080 -- in which case, is the reason it wasn't documented known? -- or is it a result of a bug in the processor implementation (presumably a microcode error that wasn't detected prior to release)?






    z80







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      down vote

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      up vote
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      down vote

      favorite











      The Z80 indirect I/O instructions are a little quirky: the instructions with the standard mnemonic in r, (c) (where r is a stand-in for any of the normal registers) actually puts the register pair bc on the address bus, not just c as implied in the mnemonic, and likewise for out (c), r. This capability is rarely used, but there are some instances (e.g. the keyboards of the ZX81 and Spectrum use the upper byte to select a row to scan) where it was used to good effect.



      Is this behaviour intentional, in order to allow the Z80 to expand beyond the 256 port limit of the 8080 -- in which case, is the reason it wasn't documented known? -- or is it a result of a bug in the processor implementation (presumably a microcode error that wasn't detected prior to release)?






      z80







      share|improve this question













      The Z80 indirect I/O instructions are a little quirky: the instructions with the standard mnemonic in r, (c) (where r is a stand-in for any of the normal registers) actually puts the register pair bc on the address bus, not just c as implied in the mnemonic, and likewise for out (c), r. This capability is rarely used, but there are some instances (e.g. the keyboards of the ZX81 and Spectrum use the upper byte to select a row to scan) where it was used to good effect.



      Is this behaviour intentional, in order to allow the Z80 to expand beyond the 256 port limit of the 8080 -- in which case, is the reason it wasn't documented known? -- or is it a result of a bug in the processor implementation (presumably a microcode error that wasn't detected prior to release)?






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      z80






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      asked 4 hours ago









      Jules

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          Well, the Z-80 CPU documentation that I have, a Zilog Z-80 product spec, PS017801-0602, clearly shows the behavior you noted in your question.



          In addition, the traditional I/O instructions, such as:



          IN A,(n)


          show the address bus as n to A0 ~ A7 and A to A8 ~ A15



          Clearly this "feature" is documented. I suspect it was just not used much.






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            Well, the Z-80 CPU documentation that I have, a Zilog Z-80 product spec, PS017801-0602, clearly shows the behavior you noted in your question.



            In addition, the traditional I/O instructions, such as:



            IN A,(n)


            show the address bus as n to A0 ~ A7 and A to A8 ~ A15



            Clearly this "feature" is documented. I suspect it was just not used much.






            share|improve this answer
























              up vote
              3
              down vote













              Well, the Z-80 CPU documentation that I have, a Zilog Z-80 product spec, PS017801-0602, clearly shows the behavior you noted in your question.



              In addition, the traditional I/O instructions, such as:



              IN A,(n)


              show the address bus as n to A0 ~ A7 and A to A8 ~ A15



              Clearly this "feature" is documented. I suspect it was just not used much.






              share|improve this answer






















                up vote
                3
                down vote










                up vote
                3
                down vote









                Well, the Z-80 CPU documentation that I have, a Zilog Z-80 product spec, PS017801-0602, clearly shows the behavior you noted in your question.



                In addition, the traditional I/O instructions, such as:



                IN A,(n)


                show the address bus as n to A0 ~ A7 and A to A8 ~ A15



                Clearly this "feature" is documented. I suspect it was just not used much.






                share|improve this answer












                Well, the Z-80 CPU documentation that I have, a Zilog Z-80 product spec, PS017801-0602, clearly shows the behavior you noted in your question.



                In addition, the traditional I/O instructions, such as:



                IN A,(n)


                show the address bus as n to A0 ~ A7 and A to A8 ~ A15



                Clearly this "feature" is documented. I suspect it was just not used much.







                share|improve this answer












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                answered 1 hour ago









                Peter Camilleri

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