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Is there a lower limit on operating frequency of CMOS SRAM?
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I study computer science, and so I am in the deep end here.
I have set upon designing a machine which requires RAM. I found a listing for Toshiba's 128KB (8 bit per word) SRAM (TC551001BPL).
I intend to run this at a very slow clock, maybe 1-10kHz or so (maybe even single stepping it with a button). Due to this I figure that I never have to worry about any sort of transition, propogation, etc times, as a clock cycle of 100 microseconds is orders of magnitude higher than the timings of any chips today, which is usually in 10's of nanoseconds (bus transcievers, D-Flip Flops, binary counters, RAM, etc). However, this made me wonder, is there a minimum frequency at which I must operate the RAM? I could not find anything like that in the datasheet, but I'm still not sure.
Could the fact that this RAM is asynchronous cause this issue?
This is slightly off topic, but I only need 1024 word, 8 bit word of RAM or so. Any IC recommendations that better suit my application would be extremely helpful.
integrated-circuit ram
asked Aug 7 at 16:38
user1512179
1512
add a comment |Â
up vote
6
down vote
favorite
I study computer science, and so I am in the deep end here.
I have set upon designing a machine which requires RAM. I found a listing for Toshiba's 128KB (8 bit per word) SRAM (TC551001BPL).
I intend to run this at a very slow clock, maybe 1-10kHz or so (maybe even single stepping it with a button). Due to this I figure that I never have to worry about any sort of transition, propogation, etc times, as a clock cycle of 100 microseconds is orders of magnitude higher than the timings of any chips today, which is usually in 10's of nanoseconds (bus transcievers, D-Flip Flops, binary counters, RAM, etc). However, this made me wonder, is there a minimum frequency at which I must operate the RAM? I could not find anything like that in the datasheet, but I'm still not sure.
Could the fact that this RAM is asynchronous cause this issue?
This is slightly off topic, but I only need 1024 word, 8 bit word of RAM or so. Any IC recommendations that better suit my application would be extremely helpful.
integrated-circuit ram
asked Aug 7 at 16:38
user1512179
1512
There are few legitimate reasons to build this with a distinct IC for computer science purposes. This little an amount of memory would be integrated right alongside the computational logic. A typically FPGA's internal resources would far exceed your need (if it's an atypical computation), or an MCU's (if it's a typical one) or you'd just do the whole thing in simulation.
– Chris Stratton
Aug 8 at 14:20
add a comment |Â
up vote
6
down vote
favorite
up vote
6
down vote
favorite
I study computer science, and so I am in the deep end here.
I have set upon designing a machine which requires RAM. I found a listing for Toshiba's 128KB (8 bit per word) SRAM (TC551001BPL).
I intend to run this at a very slow clock, maybe 1-10kHz or so (maybe even single stepping it with a button). Due to this I figure that I never have to worry about any sort of transition, propogation, etc times, as a clock cycle of 100 microseconds is orders of magnitude higher than the timings of any chips today, which is usually in 10's of nanoseconds (bus transcievers, D-Flip Flops, binary counters, RAM, etc). However, this made me wonder, is there a minimum frequency at which I must operate the RAM? I could not find anything like that in the datasheet, but I'm still not sure.
Could the fact that this RAM is asynchronous cause this issue?
This is slightly off topic, but I only need 1024 word, 8 bit word of RAM or so. Any IC recommendations that better suit my application would be extremely helpful.
integrated-circuit ram
asked Aug 7 at 16:38
user1512179
1512
I study computer science, and so I am in the deep end here.
I have set upon designing a machine which requires RAM. I found a listing for Toshiba's 128KB (8 bit per word) SRAM (TC551001BPL).
I intend to run this at a very slow clock, maybe 1-10kHz or so (maybe even single stepping it with a button). Due to this I figure that I never have to worry about any sort of transition, propogation, etc times, as a clock cycle of 100 microseconds is orders of magnitude higher than the timings of any chips today, which is usually in 10's of nanoseconds (bus transcievers, D-Flip Flops, binary counters, RAM, etc). However, this made me wonder, is there a minimum frequency at which I must operate the RAM? I could not find anything like that in the datasheet, but I'm still not sure.
Could the fact that this RAM is asynchronous cause this issue?
This is slightly off topic, but I only need 1024 word, 8 bit word of RAM or so. Any IC recommendations that better suit my application would be extremely helpful.
integrated-circuit ram
asked Aug 7 at 16:38
user1512179
1512
asked Aug 7 at 16:38
user1512179
1512
asked Aug 7 at 16:38
user1512179
1512
asked Aug 7 at 16:38
user1512179
1512
1512
There are few legitimate reasons to build this with a distinct IC for computer science purposes. This little an amount of memory would be integrated right alongside the computational logic. A typically FPGA's internal resources would far exceed your need (if it's an atypical computation), or an MCU's (if it's a typical one) or you'd just do the whole thing in simulation.
– Chris Stratton
Aug 8 at 14:20
add a comment |Â
There are few legitimate reasons to build this with a distinct IC for computer science purposes. This little an amount of memory would be integrated right alongside the computational logic. A typically FPGA's internal resources would far exceed your need (if it's an atypical computation), or an MCU's (if it's a typical one) or you'd just do the whole thing in simulation.
– Chris Stratton
Aug 8 at 14:20
There are few legitimate reasons to build this with a distinct IC for computer science purposes. This little an amount of memory would be integrated right alongside the computational logic. A typically FPGA's internal resources would far exceed your need (if it's an atypical computation), or an MCU's (if it's a typical one) or you'd just do the whole thing in simulation.
– Chris Stratton
Aug 8 at 14:20
There are few legitimate reasons to build this with a distinct IC for computer science purposes. This little an amount of memory would be integrated right alongside the computational logic. A typically FPGA's internal resources would far exceed your need (if it's an atypical computation), or an MCU's (if it's a typical one) or you'd just do the whole thing in simulation.
– Chris Stratton
Aug 8 at 14:20
add a comment |Â
3 Answers
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up vote
20
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No, there is no minimum frequency because it's static RAM. Any digital circuit that's described as "static" doesn't have a minimum frequency - it can operate with all signals held static for an extended period of time, hence the name. "Dynamic" circuits have a minimum frequency.
Just because your circuit operates at a low frequency doesn't mean you can ignore all timings, however. You still have to meet the required setup and hold times, as well as the maximum rise and fall times. The latter usually aren't a problem if you stick to a single logic family and don't use 4000 CMOS. (74HC/HCT/LS will be just fine.)
answered Aug 7 at 16:46
Jonathan S.
1,86229
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up vote
2
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I checked a 1997 data sheet for the TC551001BPL. Cycle times for read and write cycles are given on page 4. Note that there is no maximum time specified, so you can go as slow as you like. If you step with a button, debounce the pulse carefully!
Availability of your Toshiba SRAM seem limited. A quick parametric search on DigiKey threw up the AS6C62256-55PCN from Alliance Memory. This is a 32k x 8 SRAM, is low cost, and comes in a 28 pin DIP package.
answered Aug 8 at 8:32
amb
4615
add a comment |Â
up vote
1
down vote
It is a static RAM, so no there is no minimum clock cycle.
answered Aug 7 at 16:44
EE_socal
1,0206
add a comment |Â
3 Answers
3
active
oldest
votes
3 Answers
3
active
oldest
votes
active
oldest
votes
active
oldest
votes
up vote
20
down vote
No, there is no minimum frequency because it's static RAM. Any digital circuit that's described as "static" doesn't have a minimum frequency - it can operate with all signals held static for an extended period of time, hence the name. "Dynamic" circuits have a minimum frequency.
Just because your circuit operates at a low frequency doesn't mean you can ignore all timings, however. You still have to meet the required setup and hold times, as well as the maximum rise and fall times. The latter usually aren't a problem if you stick to a single logic family and don't use 4000 CMOS. (74HC/HCT/LS will be just fine.)
answered Aug 7 at 16:46
Jonathan S.
1,86229
add a comment |Â
up vote
20
down vote
No, there is no minimum frequency because it's static RAM. Any digital circuit that's described as "static" doesn't have a minimum frequency - it can operate with all signals held static for an extended period of time, hence the name. "Dynamic" circuits have a minimum frequency.
Just because your circuit operates at a low frequency doesn't mean you can ignore all timings, however. You still have to meet the required setup and hold times, as well as the maximum rise and fall times. The latter usually aren't a problem if you stick to a single logic family and don't use 4000 CMOS. (74HC/HCT/LS will be just fine.)
answered Aug 7 at 16:46
Jonathan S.
1,86229
add a comment |Â
up vote
20
down vote
up vote
20
down vote
No, there is no minimum frequency because it's static RAM. Any digital circuit that's described as "static" doesn't have a minimum frequency - it can operate with all signals held static for an extended period of time, hence the name. "Dynamic" circuits have a minimum frequency.
Just because your circuit operates at a low frequency doesn't mean you can ignore all timings, however. You still have to meet the required setup and hold times, as well as the maximum rise and fall times. The latter usually aren't a problem if you stick to a single logic family and don't use 4000 CMOS. (74HC/HCT/LS will be just fine.)
answered Aug 7 at 16:46
Jonathan S.
1,86229
No, there is no minimum frequency because it's static RAM. Any digital circuit that's described as "static" doesn't have a minimum frequency - it can operate with all signals held static for an extended period of time, hence the name. "Dynamic" circuits have a minimum frequency.
Just because your circuit operates at a low frequency doesn't mean you can ignore all timings, however. You still have to meet the required setup and hold times, as well as the maximum rise and fall times. The latter usually aren't a problem if you stick to a single logic family and don't use 4000 CMOS. (74HC/HCT/LS will be just fine.)
answered Aug 7 at 16:46
Jonathan S.
1,86229
answered Aug 7 at 16:46
Jonathan S.
1,86229
answered Aug 7 at 16:46
Jonathan S.
1,86229
answered Aug 7 at 16:46
Jonathan S.
1,86229
1,86229
add a comment |Â
add a comment |Â
up vote
2
down vote
I checked a 1997 data sheet for the TC551001BPL. Cycle times for read and write cycles are given on page 4. Note that there is no maximum time specified, so you can go as slow as you like. If you step with a button, debounce the pulse carefully!
Availability of your Toshiba SRAM seem limited. A quick parametric search on DigiKey threw up the AS6C62256-55PCN from Alliance Memory. This is a 32k x 8 SRAM, is low cost, and comes in a 28 pin DIP package.
answered Aug 8 at 8:32
amb
4615
add a comment |Â
up vote
2
down vote
I checked a 1997 data sheet for the TC551001BPL. Cycle times for read and write cycles are given on page 4. Note that there is no maximum time specified, so you can go as slow as you like. If you step with a button, debounce the pulse carefully!
Availability of your Toshiba SRAM seem limited. A quick parametric search on DigiKey threw up the AS6C62256-55PCN from Alliance Memory. This is a 32k x 8 SRAM, is low cost, and comes in a 28 pin DIP package.
answered Aug 8 at 8:32
amb
4615
add a comment |Â
up vote
2
down vote
up vote
2
down vote
I checked a 1997 data sheet for the TC551001BPL. Cycle times for read and write cycles are given on page 4. Note that there is no maximum time specified, so you can go as slow as you like. If you step with a button, debounce the pulse carefully!
Availability of your Toshiba SRAM seem limited. A quick parametric search on DigiKey threw up the AS6C62256-55PCN from Alliance Memory. This is a 32k x 8 SRAM, is low cost, and comes in a 28 pin DIP package.
answered Aug 8 at 8:32
amb
4615
I checked a 1997 data sheet for the TC551001BPL. Cycle times for read and write cycles are given on page 4. Note that there is no maximum time specified, so you can go as slow as you like. If you step with a button, debounce the pulse carefully!
Availability of your Toshiba SRAM seem limited. A quick parametric search on DigiKey threw up the AS6C62256-55PCN from Alliance Memory. This is a 32k x 8 SRAM, is low cost, and comes in a 28 pin DIP package.
answered Aug 8 at 8:32
amb
4615
answered Aug 8 at 8:32
amb
4615
answered Aug 8 at 8:32
amb
4615
answered Aug 8 at 8:32
amb
4615
4615
add a comment |Â
add a comment |Â
up vote
1
down vote
It is a static RAM, so no there is no minimum clock cycle.
answered Aug 7 at 16:44
EE_socal
1,0206
add a comment |Â
up vote
1
down vote
It is a static RAM, so no there is no minimum clock cycle.
answered Aug 7 at 16:44
EE_socal
1,0206
add a comment |Â
up vote
1
down vote
up vote
1
down vote
It is a static RAM, so no there is no minimum clock cycle.
answered Aug 7 at 16:44
EE_socal
1,0206
It is a static RAM, so no there is no minimum clock cycle.
answered Aug 7 at 16:44
EE_socal
1,0206
answered Aug 7 at 16:44
EE_socal
1,0206
answered Aug 7 at 16:44
EE_socal
1,0206
answered Aug 7 at 16:44
EE_socal
1,0206
1,0206
add a comment |Â
add a comment |Â
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There are few legitimate reasons to build this with a distinct IC for computer science purposes. This little an amount of memory would be integrated right alongside the computational logic. A typically FPGA's internal resources would far exceed your need (if it's an atypical computation), or an MCU's (if it's a typical one) or you'd just do the whole thing in simulation.
– Chris Stratton
Aug 8 at 14:20